71 lines
2.1 KiB
Python
71 lines
2.1 KiB
Python
from litex.gen import *
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from litex.gen.genlib.io import CRG
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from targets import *
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from litex.build.generic_platform import *
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from litex.build.xilinx.platform import XilinxPlatform
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.uart.bridge import UARTWishboneBridge
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from litescope.core.port import LiteScopeTerm
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from litescope.frontend.inout import LiteScopeInOut
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from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer
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_io = [
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("sys_clk", 0, Pins("X")),
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("sys_rst", 1, Pins("X")),
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("serial", 0,
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Subsignal("tx", Pins("X")),
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Subsignal("rx", Pins("X")),
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),
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("bus", 0, Pins(" ".join(["X" for i in range(128)])))
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]
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class CorePlatform(XilinxPlatform):
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name = "core"
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default_clk_name = "sys_clk"
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def __init__(self):
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XilinxPlatform.__init__(self, "", _io)
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def do_finalize(self, *args, **kwargs):
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pass
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class Core(SoCCore):
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platform = CorePlatform()
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csr_map = {
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"logic_analyzer": 16
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}
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csr_map.update(SoCCore.csr_map)
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def __init__(self, platform, clk_freq=100*1000000):
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self.clk_freq = clk_freq
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self.clock_domains.cd_sys = ClockDomain("sys")
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SoCCore.__init__(self, platform, clk_freq,
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cpu_type=None,
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csr_data_width=32,
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with_uart=False,
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ident="Litescope example design",
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with_timer=False
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)
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self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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self.bus = platform.request("bus")
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self.submodules.logic_analyzer = LiteScopeLogicAnalyzer((self.bus), 512, with_rle=True, with_subsampler=True)
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self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw))
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def get_ios(self):
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ios = set()
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ios = ios.union({self.cd_sys.clk,
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self.cd_sys.rst})
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ios = ios.union({self.platform.lookup_request("serial").rx,
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self.platform.lookup_request("serial").tx})
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ios = ios.union({self.bus})
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return ios
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default_subtarget = Core
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