77 lines
2.4 KiB
Python
77 lines
2.4 KiB
Python
# This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from migen import *
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from litex.build.io import CRG
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from litex.soc.integration.soc_core import SoCMini
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from litescope import LiteScopeIO, LiteScopeAnalyzer
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# LiteScope SoC ------------------------------------------------------------------------------------
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class LiteScopeSoC(SoCMini):
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def __init__(self, platform):
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sys_clk_freq = int((1e9/platform.default_clk_period))
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# SoCMini ----------------------------------------------------------------------------------
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SoCMini.__init__(self, platform, sys_clk_freq,
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csr_data_width = 32,
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with_uart = True,
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uart_name = "bridge",
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ident = "Litescope example design",
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ident_version = True,
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)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform.request(platform.default_clk_name))
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# Litescope IO -----------------------------------------------------------------------------
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self.submodules.io = LiteScopeIO(8)
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self.add_csr("io")
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for i in range(8):
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try:
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self.comb += platform.request("user_led", i).eq(self.io.output[i])
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except:
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pass
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# Litescope Analyzer -----------------------------------------------------------------------
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analyzer_groups = {}
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# Counter group
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counter = Signal(16, name_override="counter")
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zero = Signal(name_override="zero")
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self.sync += counter.eq(counter + 1)
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self.comb += zero.eq(counter == 0)
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analyzer_groups[0] = [
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zero,
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counter,
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]
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# Communication group
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analyzer_groups[1] = [
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platform.lookup_request("serial").tx,
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platform.lookup_request("serial").rx,
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self.bus.masters["uart_bridge"],
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]
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# FSM group
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fsm = FSM(reset_state="STATE1")
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self.submodules += fsm
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fsm.act("STATE1",
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NextState("STATE2")
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)
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fsm.act("STATE2",
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NextState("STATE1")
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)
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analyzer_groups[2] = [
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fsm,
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]
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# Analyzer
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512, csr_csv="test/analyzer.csv")
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self.add_csr("analyzer")
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default_subtarget = LiteScopeSoC
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