127 lines
4.4 KiB
Plaintext
127 lines
4.4 KiB
Plaintext
__ _ __ ____
|
|
/ / (_) /____ / __/______ ___ ___
|
|
/ /__/ / __/ -_)\ \/ __/ _ \/ _ \/ -_)
|
|
/____/_/\__/\__/___/\__/\___/ .__/\__/
|
|
/_/
|
|
Copyright 2012-2015 / EnjoyDigital
|
|
|
|
A small footprint and configurable embedded FPGA
|
|
logic analyzer core powered by Migen
|
|
|
|
[> Intro
|
|
---------
|
|
LiteScope is a small footprint and configurable embedded logic analyzer that you
|
|
can use in your FPGA and aims to provide a free, portable and flexible
|
|
alternative to vendor's solutions!
|
|
|
|
LiteScope is part of LiteX libraries whose aims are to lower entry level of
|
|
complex FPGA cores by providing simple, elegant and efficient implementations
|
|
of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
|
|
|
|
The core uses simple and specific streaming buses and will provides in the future
|
|
adapters to use standardized AXI or Avalon-ST streaming buses.
|
|
|
|
Since Python is used to describe the HDL, the core is highly and easily
|
|
configurable.
|
|
|
|
LiteScope is built using LiteX and uses technologies developed in partnership with
|
|
M-Labs Ltd:
|
|
- Migen enables generating HDL with Python in an efficient way.
|
|
- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
|
|
|
|
LiteScope can be used as LiteX library or can be integrated with your standard
|
|
design flow by generating the verilog rtl that you will use as a standard core.
|
|
|
|
[> Features
|
|
------------
|
|
- IO peek and poke with LiteScopeInOut
|
|
- Logic analyser with LiteScopeLogicAnalyzer:
|
|
- Various triggering modules: Term, Range, Edge (add yours! :)
|
|
- Run Length Encoder to "compress" data and increase recording depth
|
|
- Subsampling
|
|
- Storage qualifier
|
|
- Data storage in block rams
|
|
- Bridges:
|
|
- UART2Wishbone (provided by LiteScope)
|
|
- Ethernet2Wishbone ("Etherbone") (when used with LiteEth)
|
|
- PCIe2Wishbone (when used with LitePCIe)
|
|
- Exports formats: .vcd, .sr(sigrok), .csv, .py, etc...
|
|
|
|
[> Proven
|
|
----------
|
|
LiteScope has already been used to investigate issues on commercial and open-source designs.
|
|
|
|
[> Possible improvements
|
|
-------------------------
|
|
- add standardized interfaces (AXI, Avalon-ST)
|
|
- add protocols analyzers
|
|
- add signals injection/generation
|
|
- add storage in DRAM
|
|
- add storage in HDD with LiteSATA core
|
|
- ... See below Support and consulting :)
|
|
|
|
If you want to support these features, please contact us at florent [AT]
|
|
enjoy-digital.fr. You can also contact our partner on the public mailing list
|
|
devel [AT] lists.m-labs.hk.
|
|
|
|
|
|
[> Getting started
|
|
-------------------
|
|
1. Install Python3 and your vendor's software
|
|
|
|
2. Obtain LiteX and install it:
|
|
git clone https://github.com/enjoy-digital/litex --recursive
|
|
cd litex
|
|
python3 setup.py install
|
|
cd ..
|
|
|
|
3. Build and load test design:
|
|
go to example_designs/
|
|
./make.py -p [your_platform] all load-bitstream
|
|
Supported platforms are the ones already supported by Mibuild:
|
|
de0nano, m1, mixxeo, kc705, zedboard...
|
|
|
|
4. Test design:
|
|
go to test and run:
|
|
./make.py --port your_serial_port test_inout (will blink leds)
|
|
./make.py --port your_serial_port test_logic_analyzer (will capture counter)
|
|
|
|
tests can also be executed over Etherbone (provided with LiteEth):
|
|
./make.py --ip_address fpga_ip_address your_test
|
|
|
|
[> Simulations
|
|
---------------
|
|
TODO
|
|
|
|
[> Tests
|
|
---------
|
|
TODO
|
|
|
|
[> License
|
|
------------
|
|
LiteScope is released under the very permissive two-clause BSD license. Under
|
|
the terms of this license, you are authorized to use LiteScope for closed-source
|
|
proprietary designs.
|
|
Even though we do not require you to do so, those things are awesome, so please
|
|
do them if possible:
|
|
- tell us that you are using LiteScope
|
|
- cite LiteScope in publications related to research it has helped
|
|
- send us feedback and suggestions for improvements
|
|
- send us bug reports when something goes wrong
|
|
- send us the modifications and improvements you have done to LiteScope.
|
|
|
|
[> Support and consulting
|
|
--------------------------
|
|
We love open-source hardware and like sharing our designs with others.
|
|
|
|
LiteScope is mainly developed and maintained by EnjoyDigital.
|
|
|
|
If you would like to know more about LiteScope or if you are already a happy user
|
|
and would like to extend it for your needs, EnjoyDigital can provide standard
|
|
commercial support as well as consulting services.
|
|
|
|
So feel free to contact us, we'd love to work with you! (and eventually shorten
|
|
the list of the possible improvements :)
|
|
|
|
[> Contact
|
|
E-mail: florent [AT] enjoy-digital.fr |