72 lines
2.2 KiB
Python
72 lines
2.2 KiB
Python
from litex.gen import *
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from litex.gen.genlib.io import CRG
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.uart import UARTWishboneBridge
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from litescope import LiteScopeIO, LiteScopeAnalyzer
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class LiteScopeSoC(SoCCore):
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csr_map = {
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"io": 16,
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"analyzer": 17
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}
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csr_map.update(SoCCore.csr_map)
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def __init__(self, platform):
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clk_freq = int((1/(platform.default_clk_period))*1000000000)
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SoCCore.__init__(self, platform, clk_freq,
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cpu_type=None,
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csr_data_width=32,
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with_uart=False,
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ident="Litescope example design",
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with_timer=False
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)
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self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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self.submodules.crg = CRG(platform.request(platform.default_clk_name))
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self.submodules.io = LiteScopeIO(8)
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for i in range(8):
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try:
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self.comb += platform.request("user_led", i).eq(self.io.output[i])
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except:
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pass
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# use name override to keep naming in capture
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counter = Signal(4, name_override="counter")
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counter0 = Signal(name_override="counter0")
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counter1 = Signal(name_override="counter1")
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counter2 = Signal(name_override="counter2")
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counter3 = Signal(name_override="counter3")
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self.sync += counter.eq(counter + 1)
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self.comb += [
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counter0.eq(counter[0]),
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counter1.eq(counter[1]),
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counter2.eq(counter[2]),
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counter3.eq(counter[3]),
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]
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# group for vcd capture
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vcd_group = [
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counter
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]
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# group for sigrok capture (no bus support)
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sigrok_group = [
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counter0,
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counter1,
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counter2,
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counter3
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]
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analyzer_signals = {
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0 : vcd_group,
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1 : sigrok_group
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}
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
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def do_exit(self, vns):
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self.analyzer.export_csv(vns, "test/analyzer.csv")
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default_subtarget = LiteScopeSoC
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