mirror of
https://github.com/enjoy-digital/litescope.git
synced 2025-01-04 09:52:27 -05:00
b1b9e61ecf
use new LiteX features and only keep one trigger, subsampler, cdc, converter and storage modules. software still needs to be cleaned up.
46 lines
1.4 KiB
Python
46 lines
1.4 KiB
Python
from litex.gen import *
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from litex.gen.genlib.io import CRG
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.uart.bridge import UARTWishboneBridge
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from litescope import LiteScopeIO, LiteScopeAnalyzer
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class LiteScopeSoC(SoCCore):
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csr_map = {
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"io": 16,
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"analyzer": 17
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}
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csr_map.update(SoCCore.csr_map)
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def __init__(self, platform):
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clk_freq = int((1/(platform.default_clk_period))*1000000000)
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SoCCore.__init__(self, platform, clk_freq,
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cpu_type=None,
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csr_data_width=32,
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with_uart=False,
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ident="Litescope example design",
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with_timer=False
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)
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self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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self.submodules.crg = CRG(platform.request(platform.default_clk_name))
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self.submodules.io = LiteScopeIO(8)
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for i in range(8):
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try:
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self.comb += platform.request("user_led", i).eq(self.io.output[i])
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except:
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pass
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counter = Signal(16)
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self.sync += counter.eq(counter + 1)
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toto = Signal()
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self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
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def do_exit(self, vns):
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self.analyzer.export_csv(vns, "test/analyzer.csv")
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default_subtarget = LiteScopeSoC
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