156 lines
4.9 KiB
Python
Executable File
156 lines
4.9 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2019 kees.jongenburger <kees.jongenburger@gmail.com>
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# License: BSD
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import sys
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from migen import *
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from migen.genlib.io import CRG, DifferentialInput
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from litex.build.generic_platform import *
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from litex.build.tools import write_to_file
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from litex.boards.platforms import arty
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.uart import UARTWishboneBridge
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from litex.soc.cores.clock import *
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from litex.soc.integration import export
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from litescope import LiteScopeIO, LiteScopeAnalyzer
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#
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# Use the 8 input on the dual PMOD connector B as input
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# Those are the fast and not so well protected pins.
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_serdes_io = [
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("serdes_io", 0,
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Subsignal("d0", Pins("E15"),IOStandard("LVCMOS33")),
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Subsignal("d1", Pins("E16"),IOStandard("LVCMOS33")),
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Subsignal("d2", Pins("D15"),IOStandard("LVCMOS33")),
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Subsignal("d3", Pins("C15"),IOStandard("LVCMOS33")),
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Subsignal("d4", Pins("J17"),IOStandard("LVCMOS33")),
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Subsignal("d5", Pins("J18"),IOStandard("LVCMOS33")),
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Subsignal("d6", Pins("K15"),IOStandard("LVCMOS33")),
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Subsignal("d7", Pins("J15"),IOStandard("LVCMOS33")),
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)
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]
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class SerdesInputSignal(Module):
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def __init__(self, pad):
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self.signals = Signal(8)
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#
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# Based on a 100MHz input clock and a 400MHz sample clock and
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# Measuring at ddr speed we are sampling at 800Mhz
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#
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self.specials += Instance("ISERDESE2",
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p_DATA_WIDTH=8, p_DATA_RATE="DDR",
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p_SERDES_MODE="MASTER", p_INTERFACE_TYPE="NETWORKING",
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p_NUM_CE=1, p_IOBDELAY="NONE",
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i_D=pad,
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i_CE1=1,
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i_RST=ResetSignal("sys"),
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i_CLK=ClockSignal("sys4x"), i_CLKB=~ClockSignal("sys4x"),
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i_CLKDIV=ClockSignal("sys"),
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i_BITSLIP=0,
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o_Q8=self.signals[0], o_Q7=self.signals[1],
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o_Q6=self.signals[2], o_Q5=self.signals[3],
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o_Q4=self.signals[4], o_Q3=self.signals[5],
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o_Q2=self.signals[6], o_Q1=self.signals[7]
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)
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class SerdesIO(Module):
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def __init__(self,platform):
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platform.add_extension(_serdes_io)
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pads = platform.request("serdes_io")
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self.submodules.d0 = SerdesInputSignal(pads.d0)
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self.submodules.d1 = SerdesInputSignal(pads.d1)
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self.submodules.d2 = SerdesInputSignal(pads.d2)
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self.submodules.d3 = SerdesInputSignal(pads.d3)
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self.submodules.d4 = SerdesInputSignal(pads.d4)
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self.submodules.d5 = SerdesInputSignal(pads.d5)
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self.submodules.d6 = SerdesInputSignal(pads.d6)
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self.submodules.d7 = SerdesInputSignal(pads.d7)
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platform.add_platform_command("""
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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""")
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.cd_sys.clk.attr.add("keep")
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self.cd_sys4x.clk.attr.add("keep")
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(~platform.request("cpu_reset"))
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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class LiteScopeSoC(SoCCore):
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csr_map = {
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"analyzer": 17
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}
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csr_map.update(SoCCore.csr_map)
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def __init__(self, platform):
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sys_clk_freq = int(100e6)
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SoCCore.__init__(self, platform, sys_clk_freq,
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cpu_type=None,
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csr_data_width=32,
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with_uart=False,
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ident="Fast scope", ident_version=True,
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with_timer=False
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)
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self.submodules.serdes = SerdesIO(platform)
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# crg
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self.submodules.crg = _CRG(platform,sys_clk_freq)
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# bridge
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bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200)
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self.submodules.bridge = bridge
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self.add_wb_master(bridge.wishbone)
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# Litescope Analyzer
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analyzer_groups = {}
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# Analyzer group
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analyzer_groups[0] = [
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self.serdes.d0.signals,
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self.serdes.d1.signals,
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self.serdes.d2.signals,
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self.serdes.d3.signals,
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]
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# analyzer
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512)
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def do_exit(self, vns):
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self.analyzer.export_csv(vns, "test/analyzer.csv")
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platform = arty.Platform()
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soc = LiteScopeSoC(platform)
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vns = platform.build(soc, run="no-compile" not in sys.argv[1:])
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#
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# Create csr and analyzer files
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#
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soc.finalize()
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csr_csv = export.get_csr_csv(soc.csr_regions, soc.constants)
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write_to_file("test/csr.csv", csr_csv)
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soc.do_exit(vns)
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