50 lines
1.3 KiB
Python
50 lines
1.3 KiB
Python
# This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from migen import *
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from targets import *
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from litex.build.generic_platform import *
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from litex.build.xilinx.platform import XilinxPlatform
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from litex.soc.integration.soc_core import SoCMini
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from litescope import LiteScopeAnalyzer
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_io = [
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("sys_clock", 0, Pins(1)),
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("sys_reset", 1, Pins(1)),
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("serial", 0,
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Subsignal("tx", Pins(1)),
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Subsignal("rx", Pins(1)),
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),
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("bus", 0, Pins(128))
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]
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class CorePlatform(XilinxPlatform):
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name = "core"
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def __init__(self):
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XilinxPlatform.__init__(self, "", _io)
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class Core(SoCMini):
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platform = CorePlatform()
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def __init__(self, platform, clk_freq=100*1000000):
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self.clock_domains.cd_sys = ClockDomain("sys")
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self.comb += [
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self.cd_sys.clk.eq(platform.request("sys_clock")),
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self.cd_sys.rst.eq(platform.request("sys_reset"))
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]
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SoCMini.__init__(self, platform, clk_freq, csr_data_width=32,
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with_uart=True, uart_name="bridge",
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ident="Litescope example design", ident_version=True,
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)
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self.submodules.analyzer = LiteScopeAnalyzer(platform.request("bus"), 512)
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self.add_csr("analyzer")
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default_subtarget = Core
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