62 lines
1.6 KiB
Python
62 lines
1.6 KiB
Python
from migen import *
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from migen.genlib.io import CRG
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from targets import *
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from litex.build.generic_platform import *
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from litex.build.xilinx.platform import XilinxPlatform
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.uart import UARTWishboneBridge
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from litescope import LiteScopeAnalyzer
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_io = [
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("sys_clock", 0, Pins(1)),
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("sys_reset", 1, Pins(1)),
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("serial", 0,
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Subsignal("tx", Pins(1)),
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Subsignal("rx", Pins(1)),
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),
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("bus", 0, Pins(128))
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]
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class CorePlatform(XilinxPlatform):
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name = "core"
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default_clk_name = "sys_clk"
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def __init__(self):
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XilinxPlatform.__init__(self, "", _io)
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def do_finalize(self, *args, **kwargs):
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pass
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class Core(SoCCore):
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platform = CorePlatform()
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csr_map = {
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"analyzer": 16
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}
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csr_map.update(SoCCore.csr_map)
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def __init__(self, platform, clk_freq=100*1000000):
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self.clock_domains.cd_sys = ClockDomain("sys")
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self.comb += [
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self.cd_sys.clk.eq(platform.request("sys_clock")),
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self.cd_sys.rst.eq(platform.request("sys_reset"))
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]
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SoCCore.__init__(self, platform, clk_freq,
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cpu_type=None,
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csr_data_width=32,
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with_uart=False,
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ident="Litescope example design",
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with_timer=False
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)
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self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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self.bus = platform.request("bus")
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self.submodules.analyzer = LiteScopeAnalyzer((self.bus), 512)
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default_subtarget = Core
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