46 lines
1.4 KiB
Python
Executable File
46 lines
1.4 KiB
Python
Executable File
#!/usr/bin/env python3
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from litex.gen import *
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from litescope import LiteScopeAnalyzer
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class TB(Module):
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def __init__(self):
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counter = Signal(16)
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self.sync += counter.eq(counter + 1)
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self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
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def main_generator(dut):
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yield dut.analyzer.frontend.trigger.value.storage.eq(0x0080)
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yield dut.analyzer.frontend.trigger.mask.storage.eq(0xfff0)
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yield dut.analyzer.frontend.subsampler.value.storage.eq(2)
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yield
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yield dut.analyzer.storage.length.storage.eq(256)
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yield dut.analyzer.storage.offset.storage.eq(8)
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for i in range(16):
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yield
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yield dut.analyzer.storage.start.re.eq(1)
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yield
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yield dut.analyzer.storage.start.re.eq(0)
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yield
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while not (yield dut.analyzer.storage.idle.status):
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yield
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data = []
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while (yield dut.analyzer.storage.mem_valid.status):
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data.append((yield dut.analyzer.storage.mem_data.status))
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yield dut.analyzer.storage.mem_ready.re.eq(1)
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yield dut.analyzer.storage.mem_ready.r.eq(1)
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yield
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yield dut.analyzer.storage.mem_ready.re.eq(0)
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yield dut.analyzer.storage.mem_ready.r.eq(0)
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yield
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print(data)
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print(len(data))
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if __name__ == "__main__":
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tb = TB()
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generators = {"sys" : [main_generator(tb)]}
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clocks = {"sys": 10}
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run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
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