49 lines
1.3 KiB
Python
49 lines
1.3 KiB
Python
import unittest
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from litex.gen import *
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from litescope import LiteScopeAnalyzer
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#TODO:
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# - improve testing with a software model and check that the implementation
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# has a similar behaviour.
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class DUT(Module):
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def __init__(self):
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counter = Signal(16)
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self.sync += counter.eq(counter + 1)
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self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
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def main_generator(dut):
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yield from dut.analyzer.frontend.trigger.value.write(0x0080)
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yield from dut.analyzer.frontend.trigger.mask.write(0xfff0)
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yield from dut.analyzer.frontend.subsampler.value.write(2)
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yield
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yield from dut.analyzer.storage.length.write(256)
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yield from dut.analyzer.storage.offset.write(8)
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for i in range(16):
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yield
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yield from dut.analyzer.storage.start.write(1)
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yield
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while not (yield from dut.analyzer.storage.idle.read()):
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yield
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data = []
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while (yield from dut.analyzer.storage.mem_valid.read()):
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data.append((yield from dut.analyzer.storage.mem_data.read()))
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yield from dut.analyzer.storage.mem_ready.write(1)
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yield
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print(data)
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print(len(data))
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class TestAnalyzer(unittest.TestCase):
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def test(self):
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dut = DUT()
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generators = {"sys" : [main_generator(dut)]}
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clocks = {"sys": 10}
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run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
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