91 lines
3.7 KiB
Python
91 lines
3.7 KiB
Python
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#
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# This file is part of LiteX-Boards.
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# FPGA Board Info : https://shop.trenz-electronic.de/de/TE0890-01-P1C-5-A-S7-Mini-Fully-Open-Source-Modul-mit-AMD-Spartan-7-7S25-64-Mbit-HyperRAM?c=525
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#
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# Copyright (c) 2024 Philip Kirkpatrick <s.philip.kirkpatrick@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk100", 0, Pins("L5"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("B10"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("D14"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("A5")),
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Subsignal("rx", Pins("A12")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("C11")),
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Subsignal("clk", Pins("A8")),
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Subsignal("mosi", Pins("B11")),
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Subsignal("miso", Pins("B12")),
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IOStandard("LVCMOS33"),
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),
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# HyperRAM
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("hyperram", 0,
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Subsignal("dq", Pins("P11 P12 N4 P10 P5 N10 N11 P13"), IOStandard("LVCMOS33")),
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Subsignal("rwds", Pins("P4"), IOStandard("LVCMOS33")),
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Subsignal("cs_n", Pins("P2"), IOStandard("LVCMOS33")),
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Subsignal("rst_n", Pins("P3"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("N1"), IOStandard("LVCMOS33")),
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Misc("SLEW=FAST"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("j1", " A2 C4 D4 A3 B3 C5 E4 C3",
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" B2 C1 D2 F1 B1 D1 E2 G1",
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" F3 F4 H3 J3 F2 G4 H4 J4",
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" K3 L2 M2 M4 K4 L3 M3 M5"),
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("j2", "J12 M14 K12 M12 J11 N14 K11 M11",
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"H13 J13 L12 L14 H14 J14 L13 M13",
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"F14 E12 F11 H12 G14 F12 G11 H11",
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"E11 C10 D12 E13 C12 D10 D13 F13"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, toolchain="vivado"):
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Xilinx7SeriesPlatform.__init__(self, "xc7s25ftgb196-1", _io, _connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix1 -size 8"
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" -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property CFGBVS VCCO [current_design]")
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self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
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# For some reason this board places the clock on a non clock dedicated pin.
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# Tell Vivado to ignore this and just deal with it.
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self.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk100_IBUF]")
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def create_programmer(self):
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# OpenFPGALoader doesn't have a spiOverJtag bit for the ftgb196 package, but does have one
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# for the csga225. Based on a hint from bscan_spi_bitstreams, it seems the package doesn't
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# matter, so lie here to make it work.
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# (https://github.com/quartiq/bscan_spi_bitstreams/blob/master/xilinx_bscan_spi.py#L358)
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return OpenFPGALoader(cable="ft2232", fpga_part=f"xc7s25csga225")
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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