61 lines
2.6 KiB
Python
61 lines
2.6 KiB
Python
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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# The Forest Kitten 33 is a cryptocurrency mining accelerator card from SQRL that can be repurposed
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# as a generic FPGA PCIe development board: http://www.squirrelsresearch.com/forest-kitten-33
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk200", 0,
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Subsignal("p", Pins("BC26"), IOStandard("LVDS")),
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Subsignal("n", Pins("BC27"), IOStandard("LVDS"))
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),
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("user_led", 0, Pins("BD25"), IOStandard("LVCMOS18")),
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("user_led", 1, Pins("BE26"), IOStandard("LVCMOS18")),
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("user_led", 2, Pins("BD23"), IOStandard("LVCMOS18")),
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("user_led", 3, Pins("BF26"), IOStandard("LVCMOS18")),
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("user_led", 4, Pins("BC25"), IOStandard("LVCMOS18")),
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("user_led", 5, Pins("BB26"), IOStandard("LVCMOS18")),
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("user_led", 6, Pins("BB25"), IOStandard("LVCMOS18")),
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("i2c",
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Subsignal("scl", Pins("BB24"), IOStandard("LVCMOS18"), Misc("DRIVE=8")),
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Subsignal("sda", Pins("BA24"), IOStandard("LVCMOS18"), Misc("DRIVE=8")),
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),
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("pcie_x16", 0,
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Subsignal("rst_n", Pins("BE24"), IOStandard("LVCMOS18")),
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Subsignal("clk_p", Pins("AD9")),
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Subsignal("clk_n", Pins("AD8")),
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Subsignal("rx_p", Pins("AL2 AM4 AK4 AN2 AP4 AR2 AT4 AU2 AV4 AW2 BA2 BC2 AY4 BB4 BD4 BE6")),
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Subsignal("rx_n", Pins("AL1 AM3 AK3 AN1 AP3 AR1 AT3 AU1 AV3 AW1 BA1 BC1 AY3 BB3 BD3 BE5")),
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Subsignal("tx_p", Pins("Y5 AA7 AB5 AC7 AD5 AF5 AE7 AH5 AG7 AJ7 AL7 AM9 AN7 AP9 AR7 AT9")),
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Subsignal("tx_n", Pins("Y4 AA6 AB4 AC6 AD4 AF4 AE6 AH4 AG6 AJ6 AL6 AM8 AN6 AP8 AR6 AT8")),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk200"
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default_clk_period = 1e9/200e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xcvu33p-fsvh2104-2L-e", _io, toolchain="vivado")
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
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# Shutdown on overheatng
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self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]")
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# Reduce programming time
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self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]")
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