215 lines
8.3 KiB
Python
215 lines
8.3 KiB
Python
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) Lone Dynamics Corporation <info@lonedynamics.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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import os
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import sys
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import json
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import machdyne_vivaldi_ml1
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from litex.build.io import DDROutput
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.soc.cores.clock import *
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from litex.soc.cores.usb_ohci import USBOHCI
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.interconnect.csr_eventmanager import *
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from litedram.modules import W9825G6KH6
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from litex.soc.integration.soc import SoCRegion
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# CRG ---------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, sdram_rate):
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self.rst = Signal()
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self.cd_por = ClockDomain()
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self.cd_sys = ClockDomain()
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self.cd_init = ClockDomain()
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self.cd_video = ClockDomain()
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self.cd_video5x = ClockDomain()
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self.cd_eth = ClockDomain()
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self.stop = Signal()
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self.reset = Signal()
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# Clk / Rst
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clk48 = platform.request("clk48")
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clk50 = platform.request("clk50")
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk48)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | self.rst)
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_ps = ClockDomain()
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
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elif sdram_rate == "1:4":
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self.cd_sys2x = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_ps = ClockDomain()
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_ps, 4*sys_clk_freq, phase=180)
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else:
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self.cd_sys_ps = ClockDomain()
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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if sdram_rate == "1:2":
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sdram_clk = ClockSignal("sys2x_ps")
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elif sdram_rate == "1:4":
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sdram_clk = ClockSignal("sys4x_ps")
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else:
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sdram_clk = ClockSignal("sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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pll2 = ECP5PLL()
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self.pll2 = pll2
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pll2.register_clkin(clk50, 50e6)
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pll2.create_clkout(self.cd_eth, 50e6)
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pll2.create_clkout(self.cd_video, 25e6)
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pll2.create_clkout(self.cd_video5x, 125e6)
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self.comb += pll2.reset.eq(~por_done)
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pll3 = ECP5PLL()
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self.pll3 = pll3
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pll3.register_clkin(clk48, 48e6)
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self.cd_usb_12 = ClockDomain()
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self.cd_usb = ClockDomain()
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self.cd_usb_48 = ClockDomain()
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self.cd_usb_48 = self.cd_usb
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pll3.create_clkout(self.cd_usb, 48e6)
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pll3.create_clkout(self.cd_usb_12, 12e6)
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self.comb += pll3.reset.eq(~por_done)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {**SoCCore.mem_map, **{
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"usb_ohci": 0xc0000000,
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}}
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def __init__(self, revision="v2", device="45F", sdram_rate="1:2", sys_clk_freq=int(48e6), toolchain="trellis", with_usb_host=False, with_ethernet=False, **kwargs):
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platform = machdyne_vivaldi_ml1.Platform(revision=revision, device=device ,toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Vivaldi ML1", **kwargs)
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# DRAM -------------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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if sdram_rate == "1:2":
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sdrphy_cls = HalfRateGENSDRPHY
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elif sdram_rate == "1:4":
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sdrphy_cls = QuarterRateGENSDRPHY
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else:
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sdrphy_cls = GENSDRPHY
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self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = W9825G6KH6(sys_clk_freq, sdram_rate),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# USB Host ---------------------------------------------------------------------------------
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if with_usb_host:
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self.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6))
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self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False))
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self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
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self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet:
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from liteeth.phy.rmii import LiteEthPHYRMII
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self.ethphy = LiteEthPHYRMII(
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clock_pads=None,
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pads = platform.request("eth", 0),
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with_hw_init_reset=True,
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refclk_cd="eth")
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self.add_csr("ethphy")
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self.add_ethernet(name="ethmac", phy=self.ethphy,
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phy_cd="ethphy_eth")
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self.ethphy1 = LiteEthPHYRMII(
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clock_pads=None,
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pads = platform.request("eth", 1),
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with_hw_init_reset=True,
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refclk_cd="eth")
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self.add_csr("ethphy1")
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self.add_ethernet(name="ethmac1", phy=self.ethphy1,
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phy_cd="ethphy1_eth")
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=machdyne_vivaldi_ml1.Platform, description="LiteX SoC on Vivaldi ML1")
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parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
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parser.add_argument("--revision", default="v2", help="Board Revision (v0, v1, v2).")
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parser.add_argument("--device", default="45F", help="ECP5 device (12F, 25F, 45F or 85F).")
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parser.add_argument("--cable", default="dirtyJtag", help="Specify an openFPGALoader cable.")
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parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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parser.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable ethernet support.")
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parser.add_argument("--boot-from-flash", action="store_true", help="Boot from flash MMOD.")
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args = parser.parse_args()
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soc = BaseSoC(
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toolchain = args.toolchain,
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revision = args.revision,
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device = args.device,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_usb_host = args.with_usb_host,
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with_ethernet = args.with_ethernet,
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**parser.soc_argdict)
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if args.with_sdcard:
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soc.add_sdcard()
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer(cable=args.cable)
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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