79 lines
3.3 KiB
Python
79 lines
3.3 KiB
Python
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.efinix.platform import EfinixPlatform
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from litex.build.efinix import EfinixProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk25", 0, Pins("L17"), IOStandard("1.8_V_LVCMOS")),
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("clk100", 0, Pins("U4"), IOStandard("3.3_V_LVCMOS")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("E9")),
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Subsignal("rx", Pins("E10")),
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IOStandard("3.3_V_LVTTL"), Misc("WEAK_PULLUP")
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),
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# Buttons
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("user_btn", 0, Pins("U19"), IOStandard("3.3_V_LVCMOS")),
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]
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# Bank voltage ---------------------------------------------------------------------------------------
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_bank_info = [
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("2A" , "1.8 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="2A_MODE_SEL"/>
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("2B" , "1.8 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="2B_MODE_SEL"/>
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("2C" , "1.8 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="2C_MODE_SEL"/>
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("2D" , "1.8 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="2D_MODE_SEL"/>
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("2E" , "1.8 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="2E_MODE_SEL"/>
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("4A_4B" , "1.8 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="4A_4B_MODE_SEL"/>
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("4C" , "1.8 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="4C_MODE_SEL"/>
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("4D" , "1.8 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="4D_MODE_SEL"/>
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("BL2_BL3" , "3.3 V LVCMOS"), # is_dyn_voltage="false">
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("BR0" , "3.3 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="BR0_MODE_SEL"/>
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("BR3_BR4" , "3.3 V LVCMOS"), # is_dyn_voltage="false">
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("TL1_TL5" , "3.3 V LVCMOS"), # is_dyn_voltage="false">
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("TR0" , "3.3 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="TR0_MODE_SEL"/>
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("TR1" , "3.3 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="TR1_MODE_SEL"/>
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("TR2" , "3.3 V LVCMOS"), # is_dyn_voltage="false" mode_sel_name="TR2_MODE_SEL"/>
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("pmod0", "G15 G16 F16 F17 G17 A11 A13 A12"),
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("pmod1", "B12 C14 C13 C12 D12 F12 D13 E13"),
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]
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# PMODS --------------------------------------------------------------------------------------------
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def raw_pmod_io(pmod):
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return [(pmod, 0, Pins(" ".join([f"{pmod}:{i:d}" for i in range(8)])), IOStandard("3.3_V_LVTTL_/_LVCMOS"))]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(EfinixPlatform):
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default_clk_name = "clk25"
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default_clk_period = 1e9/25e6
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def __init__(self, toolchain="efinity"):
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EfinixPlatform.__init__(self, "Ti375C529C4", _io, _connectors, iobank_info=_bank_info, toolchain=toolchain)
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def create_programmer(self):
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return EfinixProgrammer()
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def do_finalize(self, fragment):
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EfinixPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
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