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__ _ __ _ __ ___ __
/ / (_) /____ | |/_/___/ _ )___ ___ ________/ /__
/ /__/ / __/ -_)> </___/ _ / _ \/ _ `/ __/ _ (_-<
/____/_/\__/\__/_/|_| /____/\___/\_,_/_/ \_,_/___/
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LiteX boards files
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Copyright 2012-2020 / LiteX-Hub community
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ci: switch from Travis CI to Github Actions.
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[![](https://github.com/litex-hub/litex-boards/workflows/ci/badge.svg)](https://github.com/litex-hub/litex-boards/actions) ![License](https://img.shields.io/badge/License-BSD%202--Clause-orange.svg)
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[> Intro
--------
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<figure>
<p align="center">
<img src="https://user-images.githubusercontent.com/1450143/88511626-73792100-cfe5-11ea-8d3e-dbeea6314e15.JPG">
</p>
<figcaption>
<p align="center">
From the very tiny Fomu to large PCIe accelerator boards....
</p>
</figcaption>
</figure>
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This repository contains the platforms/targets currently supported by LiteX:
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- The platform provides the definition of the board: IOs, constraints, clocks, components + methods to load and flash the bitstream to it.
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- The target provides a LiteX base design for the board that allows you to create a SoC (with or without a CPU) and integrate easily all the base components of your board: Ethernet, DRAM, PCIe, SPIFlash, SDCard, Leds, GPIOs, etc...
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The targets can be used as a base to build more complex or custom SoCs. They are are for example directly reused by the [Linux-on-LiteX-VexRiscv](https://github.com/litex-hub/linux-on-litex-vexriscv) project that is just using a specific configuration (Linux-capable CPU, additional peripherals). Basing your design on provided targets allows to to reduce code duplication between very various projects.
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README: add links to LiteX's wiki.
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First make sure to install LiteX correctly by following the [installation guide](https://github.com/enjoy-digital/litex/wiki/Installation) and have a look at the [LiteX's wiki](https://github.com/enjoy-digital/litex/wiki) for [tutorials](https://github.com/enjoy-digital/litex/wiki/Tutorials-Resources), [examples of projects](https://github.com/enjoy-digital/litex/wiki/Projects) and more information to use/build FPGA designs with it.
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Each target provides a default configuration with a CPU, ROM, SRAM, UART, DRAM (if available), Ethernet (if available), etc... that can be simply built and loaded to the FPGA with:
$ ./target.py --build --load
You can then open a terminal on the main UART of the board and interact with the LiteX BIOS:
<p align="center"><img src="https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/bios_screenshot.png"></p>
But this is just the starting point to create your own hardware! You can then:
- Change the CPU: add `--cpu-type=lm32, microwatt, serv, rocket, etc... `
- Change the Bus standard: add `--bus-standard=wishbone, axi-lite`
- Enable components: add `--with-ethernet --with-etherbone --with-sdcard etc...`
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- [Load application code to the CPU](https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU) over UART/Ethernet/SDCard, etc...
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- Create a bridge with your computer to easily [access the main bus of your SoC](https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC).
- Add a Logic Analyzer to your SoC to easily [observe/debug your design](https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC).
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- Simulate your SoC and interact with it at decent speed with [LiteX Sim](https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_sim.py)/Verilator.
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- Integrate external cores/CPU to create your own design.
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- etc...
Please use `./target.py --help` to see the pre-built various possibilities.
Hoping you will find this useful and enjoy it, please contribute back if you make improvements that could be useful to others or find issues!
update IRC channel
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**A question or want to get in touch? Our IRC channel is [#litex at irc.libera.chat](https://web.libera.chat/#litex)**
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> **Note:** All boards with >= 32MB of memory and enough logic can be considered as Linux Capable.
[> Open-hardware boards
-----------------------
Fully open-hardware boards, the ECP5 and iCE40 ones are even usable with the open-source FPGA toolchains!
| Name | FPGA Family | FPGA device | Sys-Clk | TTY | RAM | PCIe | Ethernet | Flash | SDCard |
|--------------|---------------------|---------------|----------|------|---------------------|-----------|----------------|-------------|--------|
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| ECPIX-5 | Lattice ECP5 | LFE5UM5G-85F | 75MHz | FTDI | 16-bit 512MB DDR3 | No | 1Gbps RGMII | 16MB QSPI | Yes |
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| Fomu | Lattice iCE40 | iCE40-UP5K | 12MHz | USB | 128KB SPRAM | No | No | 16MB QSPI | No |
| HADBadge | Lattice ECP5 | LFE5U-45F | 48MHz | IOs | 8-bit 32MB SDR | No | No | 16MB QSPI | No |
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| iCEBreaker | Lattice iCE40 | iCE40-UP5K | 24MHz | FTDI | 128KB SPRAM | No | No | 16MB QSPI | No |
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| iCESugar | Lattice iCE40 | iCE40-UP5K | 24MHz | STM32| 128KB SPRAM | No | No | 8MB QSPI | No |
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| LogicBone | Lattice ECP5 | LFE5U-45F | 75MHz | FTDI | 16-bit 1GB DDR3 | No | 1Gbps RGMII | 16MB QSPI | Yes |
| MarbleMini | Xilinx Artix7 | XC7A100T | 100MHz | FTDI | 16-bit 1GB DDR3 | No | 1Gbps RGMII | 16MB QSPI | No |
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| MiniSpartan6 | Xilinx Spartan6 | XC6SLX25 | 80MHz | FTDI | 16-bit 32MB SDR | No | No | 8MB QSPI | Yes |
| NeTV2 | Xilinx Artix7 | XC7A35T | 100MHz | IOs | 32-bit 512MB DDR3 | Gen2 X4 | 100Mbps RMII | 16MB QSPI | Yes |
| OrangeCrab | Lattice ECP5 | LFE5U-25F | 48MHz | USB | 16-bit 128MB SDR | No | No | 4MB QSPI | Yes |
| Pipistrello | Xilinx Spartan6 | XC6SLX45 | 83MHz | FTDI | 16-bit 64MB LPDDR | No | No | 16MB QSPI | Yes* |
| ULX3S | Lattice ECP5 | LFE5U-45F | 50MHz | FTDI | 16-bit 32MB SDR | No | No | 4MB QSPI | Yes |
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| TrellisBoard | Lattice ECP5 | LFE5UM5G-85F | 75MHz | FTDI | 32-bit 1GB DDR3 | Gen2 X1* | 1Gbps RGMII | 16MB QSPI | Yes |
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| TinyFPGA | Lattice iCE40 | iCE40-LP8K | 16MHz | IOs | No | No | No | 16MB QSPI | No |
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\* Present on the board but not yet supported or validated with LiteX.
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[> Accelerator boards
---------------------
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PCIe accelerators boards that you could use to accelerate your applications, LiteX provides you the essential cores for it: LitePCIe and LiteDRAM along with the LiteX infrastructure to create a design and easily control it/debug it.
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| Name | FPGA Family | FPGA device | Sys-Clk | TTY | DRAM | PCIe | Flash |
|----------------|---------------------|---------------|----------|------|-----------------------|---------------|-------------|
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| AcornCLE215+ | Xilinx Artix7 | XC7A200T | 125MHz | PCIe | 16-bit 1GB DDR3 | Gen2 X4 | 16MB QSPI |
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| ForestKitten33 | Xilinx Ultrascale+ | XCVU33P | 125MHz | PCIe | 2 x 1024-bit 4GB HBM2*| Gen3 X16 | ? |
| BCU1525 | Xilinx Ultrascale+ | XCVU9P | 125MHz | PCIe | 4 x 64-bit DDR4 DIMM | Gen3 X16 | ? |
| AlveoU250 | Xilinx Ultrascale+ | XCU250 | 125MHz | PCIe | 4 x 64-bit DDR4 DIMM | Gen2 X16 | ? |
update AU280 description
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| AlveoU280 | Xilinx Ultrascale+ | XCU280-ES1 | 150MHz | PCIe* | 2 x 64-bit DDR4 DIMM <BR> 2 x 1024-bit 4GB HBM2* | Gen2 X16 | ? |
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\* Present on the board but not yet supported or validated with LiteX.
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[> Repurposed hardware
----------------------
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Repurposed FPGA hardware that has been "documented" by enthusiasts :), allows you to discover FPGAs for very cheap (starting at 15$)!
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Add support for EBAZ4205 'Development' Board Usage: ``` ./ebaz4205.py --cpu-type=vexriscv --build --load ``` ``` $ pwd litex-boards/litex_boards/targets ``` Tip: Use `GTKTerm` to connect to /dev/ttyUSB0 (usually) and interact with the LiteX BIOS. References: - https://github.com/fusesoc/blinky#ebaz4205-development-board - https://github.com/olofk/serv/#ebaz4205-development-board - https://github.com/xjtuecho/EBAZ4205#ebaz4205 - https://github.com/nmigen/nmigen-boards/pull/180 (merged) - https://github.com/olofk/corescore/pull/33 - The existing 'Zybo Z7' example Note: The `PS7` stuff remains untested via LiteX for now.
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| Name | FPGA Family | FPGA device | Sys-Clk | TTY | DRAM | Ethernet | Flash |
|--------------|---------------------|---------------|-----------|------|--------------------|--------------------|-------------|
| SDS1104X-E | Xilinx Zynq | XC7Z020 | 100MHz | Eth | 32-bit 256MB DDR3 | 100Mbps MII | ? |
| Colorlight5A | Lattice ECP5 | LFE5U-25F | 60MHz | IOs | 32-bit 8MB SDR | 2x 1Gbps RGMII | 4MB QSPI |
| Linsn RV901 | Xilinx Spartan6 | XC6SLX16 | 75MHz | IOs | 32-bit 8MB SDR | 2x 1Gbps RGMII | 4MB QSPI |
| PanoLogic G2 | Xilinx Spartan6 | XC6SLX100-150 | 50MHz | IOs | 32-bit 128MB DDR2 | 1Gbps GMII | 16MB QSPI |
| Camlink-4K | Lattice ECP5 | LFE5U-25F | 81MHz | IOs | 16-bit 128MB DDR3 | No | ?MB QSPI |
| EBAZ4205 | Xilinx Zynq | XC7Z010 (28k) | 33.333MHz | IOs | 256MB DDR3 | 100Mbps RMII | 128MB NAND |
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The Colorlight5A is a very nice board to start with, cheap, powerful, easy to use with the open-source toolchain, you can find a specific LiteX project [here](https://github.com/enjoy-digital/colorlite)
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\* Present on the board but not yet supported or validated with LiteX.
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[> Development boards
---------------------
add QMTECH XC7A35T core board + daughter board
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| Name | FPGA Family | FPGA device | Sys-Clk | TTY | RAM | PCIe | Ethernet | Flash | SDCard |
|----------------|---------------------|---------------|---------|------|--------------------|-----------|----------------|-------------|--------|
| AC701 | Xilinx Artix7 | XC7A200T | 100MHz | FTDI | 64-bit ?MB DDR3 | Gen2 X4 | 1Gbps RGMII | 16MB QSPI | Yes* |
| Aller | Xilinx Artix7 | XC7A200T | 100MHz | PCIe | 16-bit 256MB DDR3 | Gen2 X4 | No | 128MB QSPI | No |
| Arty(A7) | Xilinx Artix7 | XC7A35T | 100MHz | FTDI | 16-bit 256MB DDR3 | No | 100Mbps MII | 16MB QSPI | No |
| ArtyS7 | Xilinx Spartan7 | XC7S50 | 100MHz | FTDI | 16-bit 256MB DDR3 | No | No | 16MB QSPI | No |
| Avalanche | Microsemi PolarFire | MPF300TS | 100MHz | IOs | 16-bit 256MB DDR3 | No | 1Gbps RGMII* | 8MB QSPI* | No |
add info to README
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| Basys3 | Xilinx Artix7 | XC7A35T | 100MHz | FTDI | No | No | No | 4MB QSPI | No |
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| C10LPRefKit | Intel Cyclone10 | 10CL055 | 50MHz | FTDI | 16-bit 32MB SDR | No | 100Mbps MII | 16MB QSPI | No |
CYC1000: Add initial support of CYC1000 board
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| CYC1000 | Intel Cyclone10 | 10CL025 | 50MHz | FTDI | 16-bit 64MB SDR | No | No | 16MB QSPI* | No |
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| De0Nano | Intel Cyclone4 | EP4CE22F | 50MHz | FTDI | 16-bit 32MB SDR | No | No | No | No |
| De10Lite | Intel MAX10 | 10M50DA | 50MHz | IOs | 16-bit 64MB SDR | No | No | No | No |
| DECA | Intel MAX10 | 10M50DA | 50MHz | JTAG | 16-bit 512MB DDR3* | No | Yes | No | Yes |
| De10Nano | Intel Cyclone5 | 5CSEBA6 | 50MHz | IOs | 16-bit 32MB SDR | No | No | No | Yes |
| Arrow SoCKit | Intel Cyclone5 | 5CSXFC6D6F31C8| 50MHz | JTAG | 32-bit 1GB DDR3* | No | No | No | No |
| De1SoC | Intel Cyclone5 | 5CSEMA5 | 50MHz | IOs | 16-bit 64MB SDR | No | ? | ? | ? |
| De2-115 | Intel Cyclone4 | EP4CE115 | 50MHz | IOs | 16-bit 128MB SDR | No | 1Gbps GMII* | 8MB QSPI | Yes* |
| ECP5-EVN | Lattice ECP5 | LFE5UM5G-85F | 50MHz | FTDI | No | No | ? | ? | ? |
| Genesys2 | Xilinx Kintex7 | XC7K325T | 125MHz | FTDI | 32-bit 1GB DDR3 | No | 1Gbps RGMII | 32MB QSPI* | Yes |
| KC705 | Xilinx Kintex7 | XC7K325T | 125MHz | FTDI | 64-bit 1GB DDR3 | Gen2 X8** | 1Gbps GMII | 32MB QSPI* | Yes |
| KCU105 | Xilinx KintexU | XCKU40 | 125MHz | FTDI | 64-bit 1GB DDR4 | Gen3 X8** | 1Gbps-BASE-X | 64MB QSPI* | Yes |
| KX2 | Xilinx Kintex7 | XC7K160T | 125MHz | FTDI | 64-bit 1GB DDR3 | No | No | 64MB QSPI* | No |
| LiteFury | Xilinx Artix7 | XC7A100T | 100MHz | PCIe | 16-bit 512MB DDR3 | Gen2 X4 | No | 32MB QSPI* | No |
| MachXO3 | Lattice MachXO3 | LCMXO3L-6900C | 125MHz | ? | ? | No | No | ? | No |
| Mercury XU5 | Xilinx ZynqU+ | XCZU2EG | 125MHz | FTDI | 16-bit 512MB DDR4 | No | No | 64MB QSPI* | No |
| Mimas A7 | Xilinx Artix7 | XC7A50T | 100MHz | FTDI | 16-bit 256MB DDR3 | No | 1Gbps RGMII | 16MB QSPI | No |
| Nereid | Xilinx Kintex7 | XC7K160T | 100MHz | PCIe | 64-bit 4GB DDR3 | Gen2 X4 | No | 16MB QSPI | No |
| Nexys4DDR | Xilinx Artix7 | XC7A100T | 100MHz | FTDI | 16-bit 128MB DDR2 | No | 100Mbps RMII | 16MB QSPI* | Yes |
| Nexys Video | Xilinx Artix7 | XC7A200T | 100MHz | FTDI | 16-bit 512MB DDR3 | No | 1Gbps RMII | 32MB QSPI* | Yes |
| QMTech XC7A35T | Xilinx Artix7 | XC7A35T | 100MHz | FTDI | 16-bit 256MB DDR3 | No | 1Gbps GMII** | 16MB QSPI | Yes**|
Add initial RZ-EasyFPGA support! (#270)
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| RZ-EasyFPGA | Intel Cyclone4 | EP4CE6 | 25MHz | IOs | 16-bit 8MB SDR | No | No | No | No |
add QMTECH XC7A35T core board + daughter board
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| SP605 | Xilinx Spartan6 | XC6SLX45T | 100MHz | FTDI | 16-bit 128MB DDR3* | Gen1 X1* | 1Gbps GMII | 8MB QSPI* | Yes* |
| Tagus | Xilinx Artix7 | XC7A200T | 100MHz | PCIe | 16-bit 256MB DDR3 | Gen2 X1 | 1Gbps-BASE-X* | 16MB QSPI* | No |
| VC707 | Xilinx Virex7 | XC7VX485T | 125MHz | FTDI | 64-bit 1GB DDR3 | Gen3 X8* | 1Gbps GMII | 16MB QSPI* | Yes* |
| VCU118 | Xilinx VirtexU+ | XCVU9P | 125MHz | FTDI | 2 x 64-bit 4GB DDR4| Gen3 X16*| 1Gbps SGMII | 16MB QSPI* | Yes* |
| Versa ECP5 | Lattice ECP5 | LFE5UM5G-45F | 75MHz | FTDI | 16-bit 128MB DDR3 | Gen1 X1* | 1Gbps RGMII | 16MB QSPI* | No |
| ZCU104 | Xilinx ZynqU+ | XCZU7EV | 125MHz | FTDI | 64-bit 1GB DDR4 | No | 1Gbps RGMII* | 64MB QSPI* | Yes* |
Update README.md FPGA on "Zybo Z7" is a 7-Series Zynq not a Zynq Ultrascale+
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| Zybo Z7 | Xilinx Zynq | XC7Z010 | 125MHz | FTDI | 64-bit 1GB DDR4 | No | 1Gbps RGMII* | 64MB QSPI* | Yes* |
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README: update and center banner.
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\* Present on the board but not yet supported or validated with LiteX.
add QMTECH XC7A35T core board + daughter board
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\*\* available on the daughterboard