83 lines
2.8 KiB
Python
83 lines
2.8 KiB
Python
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Jakub Cabal <jakubcabal@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk12", 0, Pins("M2"), IOStandard("3.3-V LVTTL")),
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# Leds
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("user_led", 0, Pins("M6"), IOStandard("3.3-V LVTTL")),
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("user_led", 1, Pins("T4"), IOStandard("3.3-V LVTTL")),
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("user_led", 2, Pins("T3"), IOStandard("3.3-V LVTTL")),
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("user_led", 3, Pins("R3"), IOStandard("3.3-V LVTTL")),
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("user_led", 4, Pins("T2"), IOStandard("3.3-V LVTTL")),
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("user_led", 5, Pins("R4"), IOStandard("3.3-V LVTTL")),
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("user_led", 6, Pins("N5"), IOStandard("3.3-V LVTTL")),
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("user_led", 7, Pins("N3"), IOStandard("3.3-V LVTTL")),
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# Button
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("key", 0, Pins("N6"), IOStandard("3.3-V LVTTL")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("T7"), IOStandard("3.3-V LVTTL")),
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Subsignal("rx", Pins("R7"), IOStandard("3.3-V LVTTL")),
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),
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# SDR SDRAM
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("sdram_clock", 0, Pins("B14"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins(
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"A3 B5 B4 B3 C3 D3 E6 E7",
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"D6 D8 A5 E8 A2 C6")),
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Subsignal("ba", Pins("A4 B6")),
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Subsignal("cs_n", Pins("A6")),
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Subsignal("cke", Pins("F8")),
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Subsignal("ras_n", Pins("B7")),
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Subsignal("cas_n", Pins("C8")),
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Subsignal("we_n", Pins("A7")),
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Subsignal("dq", Pins(
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"B10 A10 B11 A11 A12 D9 B12 C9",
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"D11 E11 A15 E9 D14 F9 C14 A14")),
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Subsignal("dm", Pins("B13 D12")),
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IOStandard("3.3-V LVTTL")
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),
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# ECPQ
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("epcq", 0,
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Subsignal("data0", Pins("H2")),
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Subsignal("dclk", Pins("H1")),
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Subsignal("ncs0", Pins("D2")),
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Subsignal("asd0", Pins("C1")),
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IOStandard("3.3-V LVTTL")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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def __init__(self):
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AlteraPlatform.__init__(self, "10CL025YU256C8G", _io)
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def create_programmer(self):
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return USBBlaster(cable_name="Arrow-USB-Blaster")
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
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# Generate PLL clock in STA
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self.toolchain.additional_sdc_commands.append("derive_pll_clocks")
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# Calculates clock uncertainties
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self.toolchain.additional_sdc_commands.append("derive_clock_uncertainty")
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