124 lines
4.3 KiB
Python
124 lines
4.3 KiB
Python
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Nathaniel Lewis <github@nrlewis.dev>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk50", 0, Pins("P56"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("P38"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("P134"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("P133"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("P132"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("P131"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("P127"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("P126"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("P124"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("P123"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("P59")),
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Subsignal("rx", Pins("P55")),
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IOStandard("LVCMOS33")
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),
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# AVR signals
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("tx_busy", 0, Pins("P39"), IOStandard("LVCMOS33")),
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("cclk", 0, Pins("P70"), IOStandard("LVCMOS33")),
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]
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_hdmi_shield = [
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# SDRAM
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("sdram_clock", 0, Pins("P29"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
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("sdram", 0,
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Subsignal("a", Pins("P101 P102 P104 P105 P5 P6 P7 P8 P9 P10 P88 P27 P26")),
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Subsignal("dq", Pins("P75 P78 P79 P80 P34 P35 P40 P41")),
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Subsignal("ba", Pins("P85 P87")),
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Subsignal("dm", Pins("P74")),
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Subsignal("ras_n", Pins("P83")),
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Subsignal("cas_n", Pins("P82")),
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Subsignal("we_n", Pins("P81")),
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Subsignal("cs_n", Pins("P84")),
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Subsignal("cke", Pins("P30")),
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IOStandard("LVCMOS33"),
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Misc("SLEW = FAST")
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),
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# HDMI Out (HDMI 1)
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("hdmi_out", 0,
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# TODO: do clock pins need "CLOCK_DEDICATED_ROUTE = FALSE" ?
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Subsignal("clk_p", Pins("P144")),
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Subsignal("clk_n", Pins("P143")),
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Subsignal("data0_p", Pins("P142")),
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Subsignal("data0_n", Pins("P141")),
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Subsignal("data1_p", Pins("P140")),
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Subsignal("data1_n", Pins("P139")),
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Subsignal("data2_p", Pins("P138")),
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Subsignal("data2_n", Pins("P137")),
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IOStandard("TMDS_33")
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),
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# HDMI Out DDC Bus
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("hdmi_out_sda", 0, Pins("P2"), IOStandard("LVCMOS33")),
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("hdmi_out_scl", 0, Pins("P1"), IOStandard("LVCMOS33")),
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# HDMI In (HDMI 2)
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("hdmi_in", 0,
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# TODO: do clock pins need "CLOCK_DEDICATED_ROUTE = FALSE" ?
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Subsignal("clk_p", Pins("P121")),
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Subsignal("clk_n", Pins("P120")),
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Subsignal("data0_p", Pins("P119")),
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Subsignal("data0_n", Pins("P118")),
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Subsignal("data1_p", Pins("P117")),
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Subsignal("data1_n", Pins("P116")),
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Subsignal("data2_p", Pins("P115")),
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Subsignal("data2_n", Pins("P114")),
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IOStandard("TMDS_33")
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),
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# HDMI In DDC Bus
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("hdmi_in_sda", 0, Pins("P111"), IOStandard("LVCMOS33")),
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("hdmi_in_scl", 0, Pins("P112"), IOStandard("LVCMOS33")),
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]
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_sdram_shield = [
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# SDRAM
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("sdram_clock", 0, Pins("P5"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
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("sdram", 0,
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Subsignal("a", Pins("P118 P119 P120 P121 P138 P139 P140 P141 P142 P143 P137 P144 P1")),
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Subsignal("dq", Pins("P101 P102 P104 P105 P7 P8 P9 P10")),
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Subsignal("ba", Pins("P116 P117")),
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Subsignal("dm", Pins("P6")),
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Subsignal("ras_n", Pins("P114")),
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Subsignal("cas_n", Pins("P112")),
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Subsignal("we_n", Pins("P111")),
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Subsignal("cs_n", Pins("P115")),
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Subsignal("cke", Pins("P2")),
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IOStandard("LVCMOS33"),
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Misc("SLEW = FAST")
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)
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc6slx9-2-tqg144", _io)
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self.toolchain.additional_commands = ["write_bitstream -force -bin_file {build_name}"]
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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