125 lines
4.1 KiB
Python
125 lines
4.1 KiB
Python
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# This file is Copyright (c) 2019 Antti Lukats <antti.lukats@gmail.com>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk12", 0, Pins("G21"), IOStandard("3.3-V LVTTL")),
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("clk25", 0, Pins("AA12"), IOStandard("3.3-V LVTTL")),
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("user_led", 0, Pins("C18"), IOStandard("3.3-V LVTTL")),
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("user_led", 1, Pins("D19"), IOStandard("3.3-V LVTTL")),
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("user_led", 2, Pins("C19"), IOStandard("3.3-V LVTTL")),
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("user_led", 3, Pins("C17"), IOStandard("3.3-V LVTTL")),
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("user_led", 4, Pins("D18"), IOStandard("3.3-V LVTTL")),
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("cpu_reset", 0, Pins("V15"), IOStandard("3.3-V LVTTL")),
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("sw", 0, Pins("U10"), IOStandard("3.3-V LVTTL")),
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("sw", 1, Pins("U11"), IOStandard("3.3-V LVTTL")),
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("sw", 2, Pins("V11"), IOStandard("3.3-V LVTTL")),
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("sw", 3, Pins("T10"), IOStandard("3.3-V LVTTL")),
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("sw", 4, Pins("T11"), IOStandard("3.3-V LVTTL")),
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("serial", 0,
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Subsignal("tx", Pins("B21"), IOStandard("3.3-V LVTTL")),
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Subsignal("rx", Pins("C20"), IOStandard("3.3-V LVTTL")),
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),
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("sdram_clock", 0, Pins("AA3"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins(
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"V5 Y3 W6 Y4 AB5 AB6 AA6 AA7",
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"AB7 AA5 V6 AA8 AB8")),
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Subsignal("ba", Pins("Y6 V7")),
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Subsignal("cs_n", Pins("W7")),
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Subsignal("cke", Pins("AA4")),
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Subsignal("ras_n", Pins("V8")),
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Subsignal("cas_n", Pins("Y7")),
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Subsignal("we_n", Pins("W8")),
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Subsignal("dq", Pins(
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"AB16 Y17 AA16 AA19 AB18 AA20 AB19 AB20",
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"Y13 Y15 AA13 AB15 AB13 AA15 AA14 AB14")),
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Subsignal("dm", Pins("Y14 W13")),
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IOStandard("3.3-V LVTTL")
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),
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("epcs", 0,
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Subsignal("data0", Pins("K1")),
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Subsignal("dclk", Pins("K2")),
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Subsignal("ncs0", Pins("E2")),
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Subsignal("asd0", Pins("D1")),
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IOStandard("3.3-V LVTTL")
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),
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("hyperram", 0,
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Subsignal("clk", Pins("T16")),
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Subsignal("rst_n", Pins("U12")),
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Subsignal("dq", Pins("T15 W17 U14 R15 R14 V16 U16 U17")),
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Subsignal("cs_n", Pins("V13")),
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Subsignal("rwds", Pins("U13")),
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IOStandard("3.3-V LVTTL")
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),
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("gpio_leds", 0,
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Pins("AB10 AA10 AA9 Y10 W10 U9 U8 U7"),
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IOStandard("3.3-V LVTTL")
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),
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("eth_clocks", 0,
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Subsignal("tx", Pins("U21")),
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Subsignal("rx", Pins("V22")),
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IOStandard("3.3-V LVTTL"),
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),
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("eth", 0,
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Subsignal("rst_n", Pins("R19")),
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Subsignal("mdio", Pins("AA21")),
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Subsignal("mdc", Pins("AA22")),
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Subsignal("rx_dv", Pins("W21")),
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Subsignal("rx_er", Pins("V21")),
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Subsignal("rx_data", Pins("W22 W20 Y21 Y22")),
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Subsignal("tx_en", Pins("T18")),
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Subsignal("tx_data", Pins("T17 U20 U19 T20")),
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Subsignal("col", Pins("T19")),
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Subsignal("crs", Pins("R20")),
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IOStandard("3.3-V LVTTL"),
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),
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("eth_clocks", 1,
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Subsignal("tx", Pins("N16")),
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Subsignal("rx", Pins("V22")),
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IOStandard("3.3-V LVTTL"),
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),
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("eth", 1,
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Subsignal("rst_n", Pins("M21")),
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Subsignal("mdio", Pins("N20")),
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Subsignal("mdc", Pins("N18")),
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Subsignal("rx_dv", Pins("R18")),
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Subsignal("rx_er", Pins("P17")),
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Subsignal("rx_data", Pins("M20 M19 M16 N19")),
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Subsignal("tx_en", Pins("R22")),
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Subsignal("tx_data", Pins("R21 N21 M22 N22")),
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Subsignal("col", Pins("P21")),
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Subsignal("crs", Pins("P22")),
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IOStandard("3.3-V LVTTL"),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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def __init__(self):
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AlteraPlatform.__init__(self, "10CL055YU484A7G", _io)
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def create_programmer(self):
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return USBBlaster()
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