99 lines
3.8 KiB
Python
99 lines
3.8 KiB
Python
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# I (HB) used the similar de1soc board as a starting point, therefore:
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# Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
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# SocKit adaption (c) 2020 Hans Baier <hansfbaier@gmail.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen.fhdl.module import Module
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from migen.fhdl.structure import Signal, ClockDomain
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import DDROutput
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from litex.soc.cores.clock import CycloneVPLL
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from litex.soc.integration.builder import Builder, builder_args, builder_argdict
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.integration.soc_sdram import soc_sdram_argdict, soc_sdram_args
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from litex.soc.cores.led import LedChaser
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from litex_boards.platforms import arrow_sockit
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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# Clk / Rst
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clk50 = platform.request("clk50")
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# PLL
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self.submodules.pll = pll = CycloneVPLL(speedgrade="-C6")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), revisionD=False, **kwargs):
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revision = "revD" if revisionD else "revB/C"
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platform = arrow_sockit.Platform(revision)
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# Defaults to Crossover UART, because Serial is attached to the HPS
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# and thus not available to the FPGA
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if kwargs["uart_name"] == "serial":
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kwargs["uart_name"] = "crossover"
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on the Arrow SoCKit",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on SoCKit")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--revisionD", action="store_true", help="board revision D, otherwise the more widespread revision B/C is assumed")
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parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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revisionD = args.revisionD,
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**soc_sdram_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
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if __name__ == "__main__":
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main()
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