68 lines
2.0 KiB
Python
68 lines
2.0 KiB
Python
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#
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# This file is part of LiteX-Boards.
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# Copyright (c) 2018 William D. Jones <thor0505@comcast.net>
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# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2022 Lone Dynamics Corporation <info@lonedynamics.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Krote FPGA board: https://github.com/machdyne/krote
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#
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk100", 0, Pins("B6"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("E2 F1 G2 J2"), IOStandard("LVCMOS33")),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("K10"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("L10"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("K9"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("J9"), IOStandard("LVCMOS33")),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("PMODA", "E1 B1 A2 A4 D1 C1 A1 A3"),
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("PMODB", "L3 L1 H1 G3 L2 K1 J1 F2"),
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("PMODC", "A8 A10 C11 A9 D10 B11 D11"),
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("PMODD", "E9 G10 F10 H11 E11 G11 G9"),
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("PMODE", "L8 K5 K3 L5 L7 K4 K2 L4")
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]
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# Default peripherals
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serial = [
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("serial", 0,
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Subsignal("tx", Pins("PMODE:1")),
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Subsignal("rx", Pins("PMODE:2")),
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IOStandard("LVCMOS33")
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)
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, toolchain="icestorm"):
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LatticePlatform.__init__(self, "ice40-hx8k-bg121", _io, _connectors, toolchain=toolchain)
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self.add_extension(serial)
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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