69 lines
2.2 KiB
Python
69 lines
2.2 KiB
Python
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Alain Lou <alainzlou@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk50", 0, Pins("23"), IOStandard("3.3-V LVTTL")),
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# Leds
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("user_led", 0, Pins("84"), IOStandard("3.3-V LVTTL")),
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("user_led", 1, Pins("85"), IOStandard("3.3-V LVTTL")),
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("user_led", 2, Pins("86"), IOStandard("3.3-V LVTTL")),
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("user_led", 3, Pins("87"), IOStandard("3.3-V LVTTL")),
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# Serial
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("serial", 0,
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# Uses the 9 pin serial connector
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Subsignal("tx", Pins("114"), IOStandard("3.3-V LVTTL")),
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Subsignal("rx", Pins("115"), IOStandard("3.3-V LVTTL"))
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),
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# SDRAM
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("sdram_clock", 0, Pins("43"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins(
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"76 77 80 83 68 67 66 65",
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"64 60 75 59")),
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Subsignal("ba", Pins("73 74")),
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Subsignal("cs_n", Pins("72")),
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Subsignal("cke", Pins("58")),
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Subsignal("ras_n", Pins("71")),
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Subsignal("cas_n", Pins("70")),
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Subsignal("we_n", Pins("69")),
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Subsignal("dq", Pins(
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"28 30 31 32 33 34 38 39",
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"54 53 52 51 50 49 46 44")),
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Subsignal("dm", Pins("42 55")),
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IOStandard("3.3-V LVTTL")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self):
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AlteraPlatform.__init__(self, "EP4CE6E22C8", _io)
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def create_programmer(self):
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return USBBlaster()
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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# Generate PLL clock in STA
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self.toolchain.additional_sdc_commands.append("derive_pll_clocks")
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# Calculates clock uncertainties
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self.toolchain.additional_sdc_commands.append("derive_clock_uncertainty")
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