35 lines
1.2 KiB
Python
35 lines
1.2 KiB
Python
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Ilia Sergachev <ilia@sergachev.ch>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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_io = [
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("fan", 0, Pins("A12"), IOStandard("LVCMOS33")),
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# seems like there are no on-board clock sources for PL when PS is not used
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# so here a clock-capable PMOD connector pin is added as a possible clock input (not tested)
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("pmod_hda16_cc", 0, Pins("B21"), IOStandard("LVCMOS33")),
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]
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class Platform(XilinxPlatform):
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default_clk_name = 'pmod_hda16_cc'
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default_clk_period = 10.0
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def __init__(self):
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XilinxPlatform.__init__(self, "xck26-sfvc784-2lv-c", _io, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", ]
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self.default_clk_freq = 1e9 / self.default_clk_period
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment, *args, **kwargs):
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XilinxPlatform.do_finalize(self, fragment, *args, **kwargs)
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self.add_period_constraint(self.lookup_request("pmod_hda16_cc", loose=True), self.default_clk_period)
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