2021-05-04 19:43:14 -04:00
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from litex.build.generic_platform import Subsignal, Pins, IOStandard, Misc
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class QMTechDaughterboard:
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"""
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the QMTech daughterboard contains standard peripherals
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and can be used with a number of different FPGA core boards
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source: https://www.aliexpress.com/item/1005001829520314.html
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"""
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def __init__(self, io_standard) -> None:
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"""
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because the board can be used with FPGAs core boards from
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different vendors, the constructor needs the vendor specific IOStandard
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"""
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self.io = [
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("serial", 0,
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2021-11-01 22:34:25 -04:00
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Subsignal("rx", Pins("J2:16")),
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Subsignal("tx", Pins("J2:15")),
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2021-05-04 19:43:14 -04:00
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io_standard
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),
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("user_led", 0, Pins("J2:40"), io_standard),
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("user_led", 1, Pins("J2:39"), io_standard),
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("user_led", 2, Pins("J2:38"), io_standard),
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("user_led", 3, Pins("J2:37"), io_standard),
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("user_led", 4, Pins("J2:36"), io_standard),
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("user_btn", 0, Pins("J3:7"), io_standard),
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("user_btn", 1, Pins("J2:44"), io_standard),
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("user_btn", 2, Pins("J2:43"), io_standard),
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("user_btn", 3, Pins("J2:42"), io_standard),
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("user_btn", 4, Pins("J2:41"), io_standard),
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# GMII Ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("J3:22")),
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Subsignal("gtx", Pins("J3:29")),
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Subsignal("rx", Pins("J3:37")),
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io_standard
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),
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("eth", 0,
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# rst is hardwired on the board
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#Subsignal("rst_n", Pins("-")),
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Subsignal("int_n", Pins("J3:26")),
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Subsignal("mdio", Pins("J3:15")),
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Subsignal("mdc", Pins("J3:16")),
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Subsignal("rx_dv", Pins("J3:42")),
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Subsignal("rx_er", Pins("J3:32")),
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Subsignal("rx_data", Pins("J3:41 J3:40 J3:39 J3:38 J3:36 J3:35 J3:34 J3:33")),
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Subsignal("tx_en", Pins("J3:28")),
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Subsignal("tx_er", Pins("J3:17")),
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Subsignal("tx_data", Pins("J3:27 J3:25 J3:24 J3:23 J3:21 J3:20 J3:19 J3:18")),
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Subsignal("col", Pins("J3:31")),
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Subsignal("crs", Pins("J3:30")),
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io_standard
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),
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# Seven Segment
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("seven_seg_ctl", 0, Pins("J2:33"), io_standard),
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("seven_seg_ctl", 1, Pins("J2:27"), io_standard),
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("seven_seg_ctl", 2, Pins("J2:35"), io_standard),
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("seven_seg", 0, Pins("J2:31 J2:26 J2:28 J2:32 J2:34 J2:29 J2:25 J2:30"), io_standard),
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# VGA
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("vga", 0,
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Subsignal("hsync_n", Pins("J3:44")),
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Subsignal("vsync_n", Pins("J3:43")),
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Subsignal("r", Pins("J3:57 J3:56 J3:59 J3:58 J3:60")),
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Subsignal("g", Pins("J3:51 J3:50 J3:53 J3:52 J3:54 J3:55")),
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Subsignal("b", Pins("J3:46 J3:45 J3:48 J3:47 J3:49")),
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io_standard
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),
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# PullUp resistors are on the board, so we don't need them in the FPGA
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("sdcard", 0,
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Subsignal("data", Pins("J3:10 J3:9 J3:14 J3:13")),
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Subsignal("cmd", Pins("J3:12")),
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Subsignal("clk", Pins("J3:11")),
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Subsignal("cd", Pins("J3:8")),
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io_standard,
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),
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]
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connectors = [
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("pmoda", "J2:17 J2:19 J2:21 J2:23 J2:18 J2:20 J2:22 J2:24"), #J10
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("pmodb", "J2:7 J2:9 J2:11 J2:13 J2:8 J2:10 J2:12 J2:14"), #J11
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("J1", {
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3: "J2:60",
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4: "J2:59",
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5: "J2:58",
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6: "J2:57",
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7: "J2:56",
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8: "J2:55",
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9: "J2:54",
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10: "J2:53",
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11: "J2:52",
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12: "J2:51",
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13: "J2:50",
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14: "J2:49",
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15: "J2:48",
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16: "J2:47",
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17: "J2:46",
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18: "J2:45"
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}),
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]
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