131 lines
3.7 KiB
Python
131 lines
3.7 KiB
Python
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#
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# This file is part of LiteX-Boards.
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#
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# Copright (c) 2023 Lone Dynamics Corporation <info@lonedynamics.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io_vx = [
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# Clock
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("clk48", 0, Pins("A7"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("A2"), IOStandard("LVCMOS33")),
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# SDRAM
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("sdram_clock", 0, Pins("F16"), IOStandard("LVTTL33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"M13 M14 L14 L13 G12 G13 G14 G15",
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"F12 F13 T15 F14 E14")),
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Subsignal("ba", Pins("P14 N13")),
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Subsignal("cs_n", Pins("G16")),
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Subsignal("cke", Pins("F15")),
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Subsignal("ras_n", Pins("J16")),
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Subsignal("cas_n", Pins("K16")),
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Subsignal("we_n", Pins("L15")),
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Subsignal("dq", Pins(
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"R15 R16 P15 P16 N16 N14 M16 M15",
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"E16 D14 D16 C15 C16 C14 B16 B15")),
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Subsignal("dm", Pins("L16 E15")),
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IOStandard("LVTTL33")
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),
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# VGA
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("vga", 0,
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Subsignal("r", Pins("T2")),
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Subsignal("g", Pins("N1")),
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Subsignal("b", Pins("R4")),
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#Subsignal("r", Pins("T2 R1 R2")),
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#Subsignal("g", Pins("N1 P2 P1")),
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#Subsignal("b", Pins("R4 T3 T4")),
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Subsignal("hsync", Pins("P3")),
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Subsignal("vsync", Pins("R3")),
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IOStandard("LVCMOS33")
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),
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# USB-C
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("usb", 0,
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Subsignal("d_p", Pins("T6")),
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Subsignal("d_n", Pins("R6")),
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Subsignal("pullup", Pins("R7")),
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IOStandard("LVCMOS33")
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),
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# USB HOST
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("usb_host", 0,
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Subsignal("dp", Pins("B1")),
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Subsignal("dm", Pins("B2")),
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IOStandard("LVCMOS33")
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),
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# DEBUG UART ON PMODA
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("serial", 0,
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Subsignal("tx", Pins("PMODA:1")),
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Subsignal("rx", Pins("PMODA:2")),
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IOStandard("LVCMOS33")
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),
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]
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_io_v0 = [
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# SD card w/ SPI interface
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("spisdcard", 0,
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Subsignal("clk", Pins("F2")),
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Subsignal("mosi", Pins("K1")),
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Subsignal("cs_n", Pins("K2")),
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Subsignal("miso", Pins("F3")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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("spiflash", 0,
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Subsignal("cs_n", Pins("N8"), Misc("PULLMODE=UP")),
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#Subsignal("clk", Pins("N9")),
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Subsignal("miso", Pins("T7"), Misc("PULLMODE=UP")),
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Subsignal("mosi", Pins("T8"), Misc("PULLMODE=UP")),
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Misc("SLEWRATE=SLOW"),
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IOStandard("LVCMOS33"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors_vx = [
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("PMODA", "B11 B12 B13 B14 A11 A12 A13 A14"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk48"
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default_clk_period = 1e9/48e6
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def __init__(self, revision="v0", device="12F", toolchain="trellis", **kwargs):
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assert revision in ["v0", "v1"]
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assert device in ["12F", "25F", "45F", "85F"]
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self.revision = revision
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io = _io_vx
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connectors = _connectors_vx
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if revision == "v0": io += _io_v0
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LatticePlatform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
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def create_programmer(self, cable):
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return OpenFPGALoader(cable=cable)
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)
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