100 lines
3.5 KiB
Python
100 lines
3.5 KiB
Python
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#
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# This file is part of LiteX-Boards.
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# FPGA Board Info : https://shop.trenz-electronic.de/en/TE0725-03-35-2C-FPGA-Module-with-Xilinx-Artix-7-XC7A35T-2CSG324C-2-x-50-Pin-with-2.54-mm-pitch
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#
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# Copyright (c) 2021 Shinken Sanada <sanadashinken@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk100", 0, Pins("P17"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("T8"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("M16"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("L18")),
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Subsignal("rx", Pins("M18")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("L13")),
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Subsignal("clk", Pins("E9")),
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Subsignal("mosi", Pins("K17")),
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Subsignal("miso", Pins("K18")),
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Subsignal("wp", Pins("L14")),
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Subsignal("hold", Pins("M14")),
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IOStandard("LVCMOS33"),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("L13")),
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Subsignal("clk", Pins("E9")),
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Subsignal("dq", Pins("K17 K18 L14 M14")),
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IOStandard("LVCMOS33")
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),
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# HyperRAM
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("hyperram", 0,
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Subsignal("dq", Pins("E17 B17 F18 F16 G17 D18 B18 A16"), IOStandard("SSTL18_II")),
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Subsignal("rwds", Pins("E18"), IOStandard("SSTL18_II")),
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Subsignal("cs_n", Pins("D17"), IOStandard("SSTL18_II")),
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Subsignal("rst_n", Pins("J17"), IOStandard("SSTL18_II")),
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Subsignal("clk_p", Pins("A13"), IOStandard("DIFF_SSTL18_II")),
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Subsignal("clk_n", Pins("A14"), IOStandard("DIFF_SSTL18_II")),
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Misc("SLEW=FAST"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("j1", "C6 C5 B7 B6 A6 A5 D8 C7",
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"E6 E5 E7 D7 C4 B4 A4 A3",
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"B1 A1 B3 B2 D5 D4 E3 D3",
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"F4 F3 E2 D2 H2 G2 C2 C1",
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"H1 G1 F1 E1 G6 F6 J3 J2",
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"K2 K1"),
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("j2", "L1 M1 N2 N1 M3 M2 U1 V1",
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"U4 U3 U2 V2 V5 V4 R3 T3",
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"T5 T4 N5 P5 P4 P3 P2 R2",
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"M4 N4 R1 T1 M6 N6 R6 R5",
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"V7 V6 U9 V9 U7 U6 R7 T6",
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"R8"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a35tcsg324-2", _io, _connectors, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16"
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" -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property CFGBVS VCCO [current_design]")
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self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a35t.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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# "set_property SEVERITY {{Warning}} [get_drc_checks UCIO-1]"]
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