90 lines
2.7 KiB
Python
90 lines
2.7 KiB
Python
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#!/usr/bin/env python3
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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import sys
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import ecpix5
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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# Clk / Rst
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clk100 = platform.request("clk100")
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rst_n = platform.request("rst_n")
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platform.add_period_constraint(clk100, 1e9/100e6)
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | ~rst_n)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6), **kwargs):
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platform = ecpix5.Platform(toolchain="trellis")
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Load ---------------------------------------------------------------------------------------------
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def load():
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import os
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f = open("openocd.cfg", "w")
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f.write(
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"""
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interface ftdi
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ftdi_vid_pid 0x0403 0x6010
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ftdi_channel 0
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ftdi_layout_init 0x00e8 0x60eb
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reset_config none
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adapter_khz 25000
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jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
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""")
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f.close()
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os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf soc_basesoc_ecpix5/gateware/top.svf; exit\"")
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exit()
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on ECPIX-5")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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parser.add_argument("--load", action="store_true", help="load bitstream")
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args = parser.parse_args()
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if args.load:
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load()
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soc = BaseSoC(**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**trellis_argdict(args))
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if __name__ == "__main__":
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main()
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