145 lines
4.0 KiB
Python
145 lines
4.0 KiB
Python
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Lone Dynamics Corporation <info@lonedynamics.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticeECP5Platform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io_vx = [
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# Clock
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("clk48", 0, Pins("A7"), IOStandard("LVCMOS33")),
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("clk50", 0, Pins("C7"), IOStandard("LVCMOS33")),
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# SDRAM
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("sdram_clock", 0, Pins("F16"), IOStandard("LVTTL33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"M13 M14 L14 L13 G12 G13 G14 G15",
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"F12 F13 T15 F14 E14")),
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Subsignal("ba", Pins("P14 N13")),
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Subsignal("cs_n", Pins("J16")),
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Subsignal("cke", Pins("F15")),
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Subsignal("ras_n", Pins("K15")),
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Subsignal("cas_n", Pins("K16")),
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Subsignal("we_n", Pins("L15")),
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Subsignal("dq", Pins(
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"R15 R16 P16 P15 N16 N14 M16 M15",
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"E15 D16 D14 C16 C15 C14 B15 B16")),
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Subsignal("dm", Pins("L16 E16")),
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IOStandard("LVTTL33")
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),
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# I2C
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("i2c", 0,
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Subsignal("sda", Pins("A13")),
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Subsignal("scl", Pins("A11")),
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IOStandard("LVCMOS33")
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),
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# DUAL USB HOST
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("usb_host", 0,
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Subsignal("dp", Pins("A9 C8")),
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Subsignal("dm", Pins("A10 B8")),
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IOStandard("LVCMOS33")
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),
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# ETHERNET
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("eth", 0,
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Subsignal("rx_data", Pins("E4 D4"), Misc("PULLMODE=UP")),
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Subsignal("tx_data", Pins("E6 D6")),
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Subsignal("tx_en", Pins("C5")),
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Subsignal("crs_dv", Pins("A5"), Misc("PULLMODE=UP")),
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Subsignal("rst_n", Pins("B5")),
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IOStandard("LVCMOS33")
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),
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("eth", 1,
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Subsignal("rx_data", Pins("B3 A2"), Misc("PULLMODE=UP")),
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Subsignal("tx_data", Pins("A4 A3")),
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Subsignal("tx_en", Pins("R12")),
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Subsignal("crs_dv", Pins("T13"), Misc("PULLMODE=UP")),
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Subsignal("rst_n", Pins("T14")),
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IOStandard("LVCMOS33")
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),
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# SD card w/ SD-mode interface
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("sdcard", 0,
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Subsignal("cd", Pins("A6")),
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Subsignal("clk", Pins("L3")),
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Subsignal("cmd", Pins("M1")),
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Subsignal("data", Pins("L1 M2 M3 L2")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33")
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),
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# SD card w/ SPI interface
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("spisdcard", 0,
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Subsignal("clk", Pins("L3")),
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Subsignal("mosi", Pins("M1")),
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Subsignal("cs_n", Pins("L2")),
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Subsignal("miso", Pins("L1")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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_io_v0 = [
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# DEBUG UART
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("serial", 0,
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Subsignal("tx", Pins("B3")),
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Subsignal("rx", Pins("A2")),
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IOStandard("LVCMOS33")
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),
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]
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_io_v2 = [
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# DEBUG UART
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("serial", 0,
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Subsignal("tx", Pins("B4")),
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Subsignal("rx", Pins("C4")),
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IOStandard("LVCMOS33")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors_vx = [
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticeECP5Platform):
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default_clk_name = "clk48"
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default_clk_period = 1e9/48e6
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def __init__(self, revision="v2", device="45F", toolchain="trellis", **kwargs):
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assert revision in ["v0", "v1", "v2"]
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assert device in ["12F", "25F", "45F", "85F"]
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self.revision = revision
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io = _io_vx
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connectors = _connectors_vx
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if revision == "v0": io += _io_v0
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if revision == "v1": io += _io_v0
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if revision == "v2": io += _io_v2
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LatticeECP5Platform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
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def create_programmer(self, cable):
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return OpenFPGALoader(cable=cable)
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def do_finalize(self, fragment):
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LatticeECP5Platform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)
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