148 lines
6.4 KiB
Python
148 lines
6.4 KiB
Python
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Fei Gao <feig@princeton.edu>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2022 Jiajie Chen <c@jia.je>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk100_ddr4", 0,
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Subsignal("p", Pins("BH51"), IOStandard("LVDS")),
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Subsignal("n", Pins("BJ51"), IOStandard("LVDS")),
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),
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("clk100_qdr4", 0,
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Subsignal("p", Pins("BJ4"), IOStandard("LVDS")),
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Subsignal("n", Pins("BK3"), IOStandard("LVDS")),
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),
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("clk100_rld3", 0,
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Subsignal("p", Pins("F35"), IOStandard("LVDS")),
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Subsignal("n", Pins("F36"), IOStandard("LVDS")),
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),
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("cpu_reset", 0, Pins("BM29"), IOStandard("LVCMOS12")),
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# Leds
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("user_led", 0, Pins("BH24"), IOStandard("LVCMOS18")),
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("user_led", 1, Pins("BG24"), IOStandard("LVCMOS18")),
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("user_led", 2, Pins("BG25"), IOStandard("LVCMOS18")),
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("user_led", 3, Pins("BF25"), IOStandard("LVCMOS18")),
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("user_led", 4, Pins("BF26"), IOStandard("LVCMOS18")),
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("user_led", 5, Pins("BF27"), IOStandard("LVCMOS18")),
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("user_led", 6, Pins("BG27"), IOStandard("LVCMOS18")),
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("user_led", 7, Pins("BG28"), IOStandard("LVCMOS18")),
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# Serial
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("serial", 0,
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Subsignal("rx", Pins("BP26"), IOStandard("LVCMOS18")),
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Subsignal("rts", Pins("BP22"), IOStandard("LVCMOS18")),
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Subsignal("tx", Pins("BN26"), IOStandard("LVCMOS18")),
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Subsignal("cts", Pins("BP23"), IOStandard("LVCMOS18")),
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),
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("serial", 1,
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Subsignal("rx", Pins("BK28"), IOStandard("LVCMOS18")),
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Subsignal("rts", Pins("BL26"), IOStandard("LVCMOS18")),
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Subsignal("tx", Pins("BJ28"), IOStandard("LVCMOS18")),
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Subsignal("cts", Pins("BL27"), IOStandard("LVCMOS18")),
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),
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# DDR4 memory
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("ddram", 0,
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Subsignal("a", Pins(
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"BF50 BD51 BG48 BE50 BE49 BE51 BF53 BG50",
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"BF51 BG47 BF47 BG49 BF48 BF52"),
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IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("BE54 BE53"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("BG54"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("BJ54"), IOStandard("SSTL12_DCI")),
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Subsignal("cas_n", Pins("BH54"), IOStandard("SSTL12_DCI")),
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Subsignal("we_n", Pins("BG53"), IOStandard("SSTL12_DCI")),
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Subsignal("cs_n", Pins("BP49 BK48"), IOStandard("SSTL12_DCI")), # Clam-shell topology
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Subsignal("act_n", Pins("BG52"), IOStandard("SSTL12_DCI")),
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#Subsignal("ten", Pins("BJ53"), IOStandard("SSTL12_DCI")),
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#Subsignal("alert_n", Pins("BJ52"), IOStandard("SSTL12_DCI")),
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#Subsignal("par", Pins("BL48"), IOStandard("SSTL12_DCI")),
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Subsignal("dm", Pins(
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"BN42 BL47 BH42 BD41 BM28 BM34 BH32 BG29"),
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IOStandard("POD12_DCI")),
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Subsignal("dq", Pins(
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"BM45 BP44 BP47 BN45 BM44 BN44 BN47 BP43",
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"BL45 BK44 BL46 BK43 BL43 BJ44 BL42 BJ43",
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"BK41 BG44 BG42 BH44 BH45 BG45 BG43 BJ41",
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"BE43 BF42 BC42 BF43 BD42 BF45 BE44 BF46",
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"BP32 BP29 BP31 BP28 BN32 BM30 BN31 BL30",
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"BL32 BP34 BN34 BK33 BL31 BL33 BM33 BK31",
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"BJ34 BG35 BH34 BH35 BJ33 BF35 BG34 BF36",
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"BF31 BH30 BJ31 BG32 BH31 BF32 BH29 BF33"),
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IOStandard("POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_p", Pins("BN46 BK45 BH46 BE45 BN29 BL35 BK34 BJ29"),
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IOStandard("DIFF_POD12"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_n", Pins("BP46 BK46 BJ46 BE46 BN30 BM35 BK35 BK30"),
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IOStandard("DIFF_POD12"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("clk_p", Pins("BK53"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("clk_n", Pins("BK54"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("cke", Pins("BH52"), IOStandard("SSTL12_DCI")),
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Subsignal("odt", Pins("BH49"), IOStandard("SSTL12_DCI")),
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Subsignal("reset_n", Pins("BH50"), IOStandard("LVCMOS12")),
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Misc("SLEW=FAST"),
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),
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# SGMII Clock
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("eth_clocks", 0,
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Subsignal("p", Pins("BH27"), IOStandard("LVDS")),
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Subsignal("n", Pins("BJ27"), IOStandard("LVDS")),
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),
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# SGMII Ethernet
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("eth", 0,
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Subsignal("int_n", Pins("BF22"), IOStandard("LVCMOS18")),
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Subsignal("mdio", Pins("BG23"), IOStandard("LVCMOS18")),
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Subsignal("mdc", Pins("BN27"), IOStandard("LVCMOS18")),
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Subsignal("rx_p", Pins("BJ22"), IOStandard("LVDS")),
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Subsignal("rx_n", Pins("BK21"), IOStandard("LVDS")),
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Subsignal("tx_p", Pins("BG22"), IOStandard("LVDS")),
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Subsignal("tx_n", Pins("BH22"), IOStandard("LVDS")),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxUSPPlatform):
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default_clk_name = "clk100_ddr4"
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default_clk_period = 1e9/100e6
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def __init__(self, toolchain="vivado"):
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XilinxUSPPlatform.__init__(self, "xcvu37p-fsvh2892-2L-e", _io, _connectors, toolchain="vivado")
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxUSPPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100_ddr4", loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("clk100_qdr4", loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("clk100_rld3", loose=True), 1e9/100e6)
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# DDR4 memory Internal Vref
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 64]")
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]")
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]")
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# For HBM2 IP in Vivado 2019.2 (https://www.xilinx.com/support/answers/72607.html)
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self.add_platform_command("connect_debug_port dbg_hub/clk [get_nets apb_clk]")
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