targets/orangecrab: use new DM remapping capability of LiteDRAM to fix LDM/UDM.
Required by VexRiscv-SMP that uses DMs on LiteDRAM interface.
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@ -180,7 +180,8 @@ class BaseSoC(SoCCore):
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ddram_pads = platform.request("ddram")
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self.submodules.ddrphy = ECP5DDRPHY(
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pads = ddram_pads,
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sys_clk_freq = sys_clk_freq)
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sys_clk_freq = sys_clk_freq,
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dm_remapping = {0:1, 1:0})
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self.ddrphy.settings.rtt_nom = "disabled"
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self.add_csr("ddrphy")
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if hasattr(ddram_pads, "vccio"):
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