Add support for QMTech Artix7 200T FBG484 board
This commit is contained in:
Hans Baier
parent
98ddb97f5e
commit
0125ae4271
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk50", 0, Pins("W19"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("Y6"), IOStandard("LVCMOS33")),
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("prog_b", 0, Pins("N12"), IOStandard("LVCMOS33")),
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# The core board does not have a USB serial on it,
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# so you will have to attach an USB to serial adapter
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# on these pins
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("gpio_serial", 0,
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Subsignal("tx", Pins("J2:7")),
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Subsignal("rx", Pins("J2:8")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash
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# 128Mbit SPI FLASH
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("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("T19")),
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Subsignal("clk", Pins("L12")),
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Subsignal("dq", Pins("P22 R22 P21 R21")),
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IOStandard("LVCMOS33")
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),
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# DDR3 SDRAM
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# MT41K128M16JT-125K
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("ddram", 0,
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Subsignal("a", Pins("A15 D14 A14 D15 E14 F14 E13 C13 E16 B13 C17 F13 F16 A13"),
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("D16 E17 B15"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("B17"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("B16"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("A16"), IOStandard("SSTL135")),
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# cs_n is hardwired on the board
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#Subsignal("cs_n", Pins(""), IOStandard("SSTL135")),
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Subsignal("dm", Pins("F19 D20"), IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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"B20 A18 A20 D19 A19 C18 C19 E19 C20 D22 D21 E21 C22 G21 B22 E22"),
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IOStandard("SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("F18 B21"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_n", Pins("E18 A21"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("clk_p", Pins("C14"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("C15"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("B18"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("D17"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("F15"), IOStandard("SSTL135")),
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Misc("SLEW=FAST"),
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),
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]
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# The connectors are named after the daughterboard, not the core board
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# because on the different core boards the names vary, but on the
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# daughterboard they stay the same, which we need to connect the
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# daughterboard peripherals to the core board.
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# On this board J2 is U2 and J3 is U4
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_connectors = [
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("J2", {
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# odd row even row
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7: "H22", 8: "J22",
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9: "H18", 10: "H17",
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11: "K22", 12: "K21",
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13: "G20", 14: "H20",
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15: "H19", 16: "J19",
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17: "J21", 18: "J20",
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19: "J17", 20: "K17",
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21: "L20", 22: "L19",
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23: "H14", 24: "J14",
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25: "K14", 26: "K13",
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27: "M16", 28: "M15",
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29: "M20", 30: "N20",
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31: "M22", 32: "N22",
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33: "L15", 34: "L14",
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35: "N19", 36: "N18",
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37: "P17", 38: "N17",
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39: "T18", 40: "R18",
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41: "Y22", 42: "Y21",
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43: "U21", 44: "T21",
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45: "V20", 46: "U20",
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47: "U18", 48: "U17",
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49: "V19", 50: "V18",
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51: "AB22", 52: "AB21",
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53: "AA21", 54: "AA20",
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55: "AB20", 56: "AA19",
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57: "Y19", 58: "Y18",
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59: "AB18", 60: "AA18",
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}),
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("J3", {
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# odd row even row
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7: "B1", 8: "A1",
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9: "C2", 10: "B2",
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11: "E1", 12: "D1",
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13: "E2", 14: "D2",
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15: "G1", 16: "F1",
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17: "H2", 18: "G2",
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19: "K1", 20: "J1",
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21: "K2", 22: "J2",
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23: "M1", 24: "L1",
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25: "K4", 26: "J4",
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27: "L3", 28: "K3",
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29: "M3", 30: "M2",
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31: "P2", 32: "N2",
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33: "R1", 34: "P1",
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35: "P5", 36: "P4",
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37: "R4", 38: "T4",
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39: "T5", 40: "U5",
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41: "T1", 42: "U1",
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43: "W1", 44: "Y1",
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45: "AA1", 46: "AB1",
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47: "AB3", 48: "AB2",
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49: "V4", 50: "W4",
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51: "Y3", 52: "AA3",
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53: "Y4", 54: "AA4",
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55: "AA5", 56: "AB5",
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57: "AB7", 58: "AB6",
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59: "AA8", 60: "AB8",
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})
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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kgates = None
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def __init__(self, kgates=200, toolchain="vivado", with_daughterboard=False):
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assert(kgates in [100, 200], "kgates can only be 100 or 200 representing a XC7A7100T, XC7TA200T")
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self.kgates = kgates
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device = f"xc7a{kgates}tfbg484-1"
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io = _io
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connectors = _connectors
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core_leds_name = "onboard_led" if with_daughterboard else "user_led"
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io += [
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(core_leds_name, 0, Pins("F3"), IOStandard("LVCMOS33")),
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(core_leds_name, 1, Pins("E3"), IOStandard("LVCMOS33")),
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]
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if with_daughterboard:
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from litex_boards.platforms.qmtech_daughterboard import QMTechDaughterboard
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daughterboard = QMTechDaughterboard(IOStandard("LVCMOS33"))
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io += daughterboard.io
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connectors += daughterboard.connectors
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Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 16]")
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self.add_platform_command("set_property CFGBVS VCCO [current_design]")
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self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
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self.toolchain.f4pga_device = device
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def create_programmer(self):
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bscan_spi = f"bscan_spi_xc7a{self.kgates}t.bit"
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return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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@ -0,0 +1,200 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# https://www.aliexpress.com/item/1005002960622091.html
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import qmtech_artix7_fbg484
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoVGAPHY
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41J128M16
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from litedram.phy import s7ddrphy
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from liteeth.phy.mii import LiteEthPHYMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_ethernet, with_vga):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_dqs = ClockDomain()
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self.cd_idelay = ClockDomain()
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self.cd_eth = ClockDomain()
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if with_ethernet:
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self.cd_eth = ClockDomain()
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if with_vga:
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self.cd_vga = ClockDomain()
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# # #
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self.pll = pll = S7PLL(speedgrade=-1)
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try:
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reset_button = platform.request("cpu_reset")
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self.comb += pll.reset.eq(~reset_button | self.rst)
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except:
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("clk50"), 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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if with_ethernet:
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pll.create_clkout(self.cd_eth, 25e6)
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if with_vga:
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pll.create_clkout(self.cd_vga, 40e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, toolchain="vivado", kgates=200, sys_clk_freq=100e6, with_daughterboard=False,
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with_ethernet = False,
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with_etherbone = False,
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eth_ip = "192.168.1.50",
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eth_dynamic_ip = False,
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with_led_chaser = True,
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with_video_terminal = False,
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with_video_framebuffer = False,
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with_jtagbone = True,
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with_spi_flash = False,
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**kwargs):
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platform = qmtech_artix7_fbg484.Platform(kgates=kgates, toolchain=toolchain, with_daughterboard=with_daughterboard)
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq,
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with_ethernet = (with_ethernet or with_etherbone),
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with_vga = (with_video_terminal or with_video_framebuffer)
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)
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# SoCCore ----------------------------------------------------------------------------------
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if (kwargs["uart_name"] == "serial") and (not with_daughterboard):
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kwargs["uart_name"] = "gpio_serial"
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = f"LiteX SoC on QMTech XC7A{kgates}T" + (" + Daughterboard" if with_daughterboard else ""),
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**kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J128M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# The daughterboard has the tx clock wired to a non-clock pin, so we can't help it
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self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]")
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# Jtagbone ---------------------------------------------------------------------------------
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if with_jtagbone:
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self.add_jtagbone()
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import MT25QL128
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", module=MT25QL128(Codes.READ_1_1_1), with_master=True)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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self.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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if not with_daughterboard and kwargs["uart_name"] == "serial":
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kwargs["uart_name"] = "jtag_serial"
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=qmtech_artix7_fbg484.Platform, description="LiteX SoC on QMTech Artix7 FBG484.")
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parser.add_target_argument("--kgates", default=200, type=int, help="Number of kgates. Allowed values: 75, 100, 200, representing XC7A75T, XC7A100T and XC7A200T")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.")
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ethopts = parser.target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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sdopts = parser.target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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viopts = parser.target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).")
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args = parser.parse_args()
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soc = BaseSoC(
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toolchain = args.toolchain,
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kgates = args.kgates,
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sys_clk_freq = args.sys_clk_freq,
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with_daughterboard = args.with_daughterboard,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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with_jtagbone = args.with_jtagbone,
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with_spi_flash = args.with_spi_flash,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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**parser.soc_argdict
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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