targets: icebreaker: fix argument parsing for cpu

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2020-02-03 12:39:13 +08:00 committed by Piotr Esden-Tempski
parent f0dd31f6c8
commit 0185095782
1 changed files with 6 additions and 2 deletions

View File

@ -109,9 +109,13 @@ class BaseSoC(SoCCore):
# Force the SRAM size to 0, because we add our own SRAM with SPRAM
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
if debug:
kwargs["uart_name"] = "crossover"
if kwargs["cpu_type"] == "vexriscv":
kwargs["cpu_variant"] = kwargs["cpu_variant"] + "+debug"
SoCCore.__init__(self, platform, clk_freq,
with_uart=True,
with_ctrl=True,
@ -188,10 +192,10 @@ def main():
if args.cpu:
kwargs["cpu_type"] = "vexriscv"
kwargs["cpu_variant"]="min"
kwargs["cpu_variant"] = "min"
soc = BaseSoC(pnr_placer=args.placer, pnr_seed=args.seed,
debug=True, **soc_core_argdict(args))
debug=True, **kwargs)
builder = Builder(soc, **builder_argdict(args))
builder.build()