targets: icebreaker: fix argument parsing for cpu
Signed-off-by: Sean Cross <sean@xobs.io>
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@ -109,9 +109,13 @@ class BaseSoC(SoCCore):
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# Force the SRAM size to 0, because we add our own SRAM with SPRAM
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kwargs["integrated_sram_size"] = 0
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kwargs["integrated_rom_size"] = 0
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if debug:
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kwargs["uart_name"] = "crossover"
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if kwargs["cpu_type"] == "vexriscv":
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kwargs["cpu_variant"] = kwargs["cpu_variant"] + "+debug"
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SoCCore.__init__(self, platform, clk_freq,
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with_uart=True,
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with_ctrl=True,
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@ -188,10 +192,10 @@ def main():
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if args.cpu:
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kwargs["cpu_type"] = "vexriscv"
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kwargs["cpu_variant"]="min"
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kwargs["cpu_variant"] = "min"
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soc = BaseSoC(pnr_placer=args.placer, pnr_seed=args.seed,
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debug=True, **soc_core_argdict(args))
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debug=True, **kwargs)
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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