Support file for the ZTEX USB-FPGA Module 2.13
This commit is contained in:
Romain Dolbeau
parent
abccd12058
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#
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# This file is part of LiteX-Boards.
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#
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# Support for the ZTEX USB-FGPA Module 2.13:
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# <https://www.ztex.de/usb-fpga-2/usb-fpga-2.13.e.html>
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# With (no-so-optional) expansion, either the ZTEX Debug board:
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# <https://www.ztex.de/usb-fpga-2/debug.e.html>
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# Or the SBusFPGA adapter board:
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# <https://github.com/rdolbeau/SBusFPGA>
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#
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# Copyright (c) 2015 Yann Sionneau <yann.sionneau@gmail.com>
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020-2021 Romain Dolbeau <romain@dolbeau.org>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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## 48 MHz clock reference
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("clk48", 0, Pins("P15"), IOStandard("LVCMOS33")),
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## embedded 256 MiB DDR3 DRAM
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("ddram", 0,
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Subsignal("a", Pins("C5 B6 C7 D5 A3 E7 A4 C6", "A6 D8 B2 A5 B3 B7"),
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("E5 A1 E6"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("E3"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("D3"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("D4"), IOStandard("SSTL135")),
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# Subsignal("cs_n", Pins(""), IOStandard("SSTL135")),
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Subsignal("dm", Pins("G1 G6"), IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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"H1 F1 E2 E1 F4 C1 F3 D2",
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"G4 H5 G3 H6 J2 J3 K1 K2"),
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IOStandard("SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("H2 J4"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_n", Pins("G2 H4"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("clk_p", Pins("C4"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("B4"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("B1"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("F5"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("J5"), IOStandard("SSTL135")),
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Misc("SLEW=FAST"),
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),
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]
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_debug_io = [
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## leds on the debug board
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("user_led", 0, Pins("H15"), IOStandard("lvcmos33")), #LED0
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("user_led", 1, Pins("J13"), IOStandard("lvcmos33")), #LED1
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("user_led", 2, Pins("J14"), IOStandard("lvcmos33")), #LED2
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("user_led", 3, Pins("H14"), IOStandard("lvcmos33")), #LED3
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("user_led", 4, Pins("H17"), IOStandard("lvcmos33")), #LED4
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("user_led", 5, Pins("G14"), IOStandard("lvcmos33")), #LED5
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("user_led", 6, Pins("G17"), IOStandard("lvcmos33")), #LED6
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("user_led", 7, Pins("G16"), IOStandard("lvcmos33")), #LED7
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("user_led", 8, Pins("G18"), IOStandard("lvcmos33")), #LED8
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("user_led", 9, Pins("H16"), IOStandard("lvcmos33")), #LED9
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("user_led", 10, Pins("U9"), IOStandard("lvcmos33")), #LED10
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("user_led", 11, Pins("V9"), IOStandard("lvcmos33")), #LED11
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("user_led", 12, Pins("U8"), IOStandard("lvcmos33")), #LED12
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("user_led", 13, Pins("V7"), IOStandard("lvcmos33")), #LED13
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("user_led", 14, Pins("U7"), IOStandard("lvcmos33")), #LED14
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("user_led", 15, Pins("V6"), IOStandard("lvcmos33")), #LED15
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("user_led", 16, Pins("U6"), IOStandard("lvcmos33")), #LED16
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("user_led", 17, Pins("V5"), IOStandard("lvcmos33")), #LED17
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("user_led", 18, Pins("T8"), IOStandard("lvcmos33")), #LED18
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("user_led", 19, Pins("V4"), IOStandard("lvcmos33")), #LED19
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("user_led", 20, Pins("R8"), IOStandard("lvcmos33")), #LED20
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("user_led", 21, Pins("T5"), IOStandard("lvcmos33")), #LED21
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("user_led", 22, Pins("R7"), IOStandard("lvcmos33")), #LED22
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("user_led", 23, Pins("T4"), IOStandard("lvcmos33")), #LED23
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("user_led", 24, Pins("T6"), IOStandard("lvcmos33")), #LED24
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("user_led", 25, Pins("U4"), IOStandard("lvcmos33")), #LED25
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("user_led", 26, Pins("R6"), IOStandard("lvcmos33")), #LED26
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("user_led", 27, Pins("U3"), IOStandard("lvcmos33")), #LED27
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("user_led", 28, Pins("R5"), IOStandard("lvcmos33")), #LED28
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("user_led", 29, Pins("V1"), IOStandard("lvcmos33")), #LED29
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## arbitrary selection of pins for the console
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("serial", 0,
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Subsignal("tx", Pins("A13")), # A13 in B29
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Subsignal("rx", Pins("A11")), # A11 in B30
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IOStandard("LVCMOS33")
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),
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]
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_sbus_io = [
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## leds on the SBus board
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("user_led", 0, Pins("U8"), IOStandard("lvcmos33")), #LED0
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("user_led", 1, Pins("U7"), IOStandard("lvcmos33")), #LED1
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("user_led", 2, Pins("U6"), IOStandard("lvcmos33")), #LED2
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("user_led", 3, Pins("T8"), IOStandard("lvcmos33")), #LED3
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("user_led", 4, Pins("P4"), IOStandard("lvcmos33")), #LED4
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("user_led", 5, Pins("P3"), IOStandard("lvcmos33")), #LED5
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("user_led", 6, Pins("T1"), IOStandard("lvcmos33")), #LED6
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("user_led", 7, Pins("R1"), IOStandard("lvcmos33")), #LED7
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("user_led", 8, Pins("U1"), IOStandard("lvcmos33")), #SBUS_DATA_OE_LED
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("user_led", 9, Pins("T3"), IOStandard("lvcmos33")), #SBUS_DATA_OE_LED_2
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## serial header for console
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("serial", 0,
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Subsignal("tx", Pins("V9")), # FIXME: might be the other way round
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Subsignal("rx", Pins("U9")),
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IOStandard("LVCMOS33")
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),
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## sdcard connector
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("spisdcard", 0,
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Subsignal("clk", Pins("R8")),
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Subsignal("mosi", Pins("T5"), Misc("PULLUP")),
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Subsignal("cs_n", Pins("V6"), Misc("PULLUP")),
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Subsignal("miso", Pins("V5"), Misc("PULLUP")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("data", Pins("V5 V4 V7 V6"), Misc("PULLUP")),
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Subsignal("cmd", Pins("T5"), Misc("PULLUP")),
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Subsignal("clk", Pins("R8")),
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#Subsignal("cd", Pins("V6")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk48"
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default_clk_period = 1e9/48e6
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def __init__(self, variant="ztex2.13a", expansion="debug"):
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device = {
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"ztex2.13a": "xc7a35tcsg324-1",
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#"ztex2.13b": "xc7a50tcsg324-1", #untested
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#"ztex2.13b2": "xc7a50tcsg324-1", #untested
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#"ztex2.13c": "xc7a75tcsg324-2", #untested
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#"ztex2.13d": "xc7a100tcsg324-2", #untested
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}[variant]
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XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
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if (expansion == "debug"):
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self.add_extension(_debug_io)
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else:
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if (expansion == "sbus"):
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self.add_extension(_sbus_io)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]",
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]",
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"set_property BITSTREAM.GENERAL.COMPRESS true [current_design]"
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]
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def create_programmer(self):
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bscan_spi = "bscan_spi_xc7a35t.bit"
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return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi) #FIXME
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Support for the ZTEX USB-FGPA Module 2.13:
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# <https://www.ztex.de/usb-fpga-2/usb-fpga-2.13.e.html>
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# With (no-so-optional) expansion, either the ZTEX Debug board:
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# <https://www.ztex.de/usb-fpga-2/debug.e.html>
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# Or the SBusFPGA adapter board:
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# <https://github.com/rdolbeau/SBusFPGA>
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#
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020-2021 Romain Dolbeau <romain@dolbeau.org>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import ztex213
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41J128M16
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from litedram.phy import s7ddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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# # #
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clk48 = platform.request("clk48")
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self.submodules.pll = pll = S7MMCM(speedgrade=-1)
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# self.comb += pll.reset.eq(~platform.request("cpu_reset"))
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk48)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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self.comb += pll.reset.eq(~por_done)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6), expansion="debug", **kwargs):
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platform = ztex213.Platform(expansion=expansion)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Ztex 2.13",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_csr("ddrphy")
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J128M16(sys_clk_freq, "1:4"), #MT41J128M16XX-125
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x40000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Ztex 2.13")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--expansion", default="debug", help="Expansion board, 'debug' (default) or 'sbus'")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default=100MHz)")
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parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
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parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
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builder_args(parser)
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soc_sdram_args(parser)
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#soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), expansion=args.expansion, **soc_sdram_argdict(args))
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assert not (args.with_spi_sdcard and args.with_sdcard)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard() #sbus only
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if args.with_sdcard:
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soc.add_sdcard() #sbus only
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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