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de10nano: cleanup a bit, rename SDRAMSoC to MiSTerSDRAMSoC and argument to --with-mister-sdram to make it clear that it's using the MiSTer SDRAM extension board.

This commit is contained in:
Florent Kermarrec 2020-01-31 09:29:02 +01:00
parent cf9a9ff91b
commit 0627f55dca
1 changed files with 15 additions and 15 deletions
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18
litex_boards/community/targets/de10nano.py
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@ -20,7 +20,7 @@ from litedram.phy import GENSDRPHY
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(Module): class _CRG(Module):
def __init__(self, platform): def __init__(self, platform, with_sdram=False):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain()
@ -66,6 +66,7 @@ class _CRG(Module):
AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked) AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked)
] ]
if with_sdram:
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
@ -81,10 +82,9 @@ class BaseSoC(SoCCore):
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform) self.submodules.crg = _CRG(platform)
# MiSTerSDRAMSoC -----------------------------------------------------------------------------------
# SDRAMSoC ------------------------------------------------------------------------------------------ class MiSTerSDRAMSoC(SoCSDRAM):
class SDRAMSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(50e6), **kwargs): def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6) assert sys_clk_freq == int(50e6)
platform = de10nano.Platform() platform = de10nano.Platform()
@ -93,10 +93,10 @@ class SDRAMSoC(SoCSDRAM):
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform) self.submodules.crg = _CRG(platform, with_sdram=True)
# SDR SDRAM -------------------------------------------------------------------------------- # SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = AS4C16M16(self.clk_freq, "1:1") sdram_module = AS4C16M16(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy, self.register_sdram(self.sdrphy,
@ -107,14 +107,14 @@ class SDRAMSoC(SoCSDRAM):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Nano") parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Nano")
parser.add_argument("--with-sdram", action="store_true", parser.add_argument("--with-mister-sdram", action="store_true",
help="enable MiSTer SDRAM expansion board") help="enable MiSTer SDRAM expansion board")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = None soc = None
if args.with_sdram: if args.with_mister_sdram:
soc = SDRAMSoC(**soc_sdram_argdict(args)) soc = MiSTerSDRAMSoC(**soc_sdram_argdict(args))
else: else:
soc = BaseSoC(**soc_sdram_argdict(args)) soc = BaseSoC(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))