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targets/arty: add variant support through --variant args. 

./arty.py --variant=a7-35 or a7-100
./arty_s7.py --variant=s7-50 or s7-25
This commit is contained in:
Florent Kermarrec 2020-12-29 18:41:58 +01:00
parent 02a81d54e2
commit 06cb49af37
2 changed files with 8 additions and 4 deletions
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6
litex_boards/targets/arty.py
View File

@ -55,8 +55,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, ident_version=True, **kwargs):
platform = arty.Platform(toolchain=toolchain)
def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, ident_version=True, **kwargs):
platform = arty.Platform(variant=variant, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
@ -108,6 +108,7 @@ def main():
parser.add_argument("--toolchain", default="vivado", help="Toolchain use to build (default: vivado)")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--variant", default="a7-35", help="Board variant: a7-35 (default) or a7-100")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
@ -121,6 +122,7 @@ def main():
assert not (args.with_ethernet and args.with_etherbone)
soc = BaseSoC(
variant = args.variant,
toolchain = args.toolchain,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,

6
litex_boards/targets/arty_s7.py
View File

@ -51,8 +51,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = arty_s7.Platform()
def __init__(self, variant="s7-50", sys_clk_freq=int(100e6), **kwargs):
platform = arty_s7.Platform(variant=variant)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
@ -92,6 +92,7 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty S7")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--variant", default="s7-50", help="Board variant: s7-50 (default) or s7-25")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
builder_args(parser)
soc_sdram_args(parser)
@ -99,6 +100,7 @@ def main():
args = parser.parse_args()
soc = BaseSoC(
variant = args.variant,
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_sdram_argdict(args)
)