Merge branch 'master' into vc707_clk

litex_boards/platforms/arrow_sockit.py

@@ -147,26 +147,33 @@ _io = [
         Subsignal("aud_i2c_sdat", Pins("AF30")),
         Subsignal("aud_mute",     Pins("AD26")),
         IOStandard("3.3-V LVTTL")
-    )
+    ),
+
+    ("gpio_serial", 0,
+        Subsignal("tx", Pins("J3:9")),
+        Subsignal("rx", Pins("J3:10")),
+        IOStandard("3.3-V LVTTL"))
 ]
 
 # Connectors ---------------------------------------------------------------------------------------
-
+# Since the numbering of the connectors in the documentation is 1-based
+# I added a dummy pin (-) to the beginning to each connector
+# to make the numbering in the code consistent with the documentation
 _connectors_hsmc_gpio_daughterboard = [
-    ("J2", "G15 F14 H15 F15 A13 G13 B13 H14 B11 E13 - - " +
+    ("J2", "- G15 F14 H15 F15 A13 G13 B13 H14 B11 E13 - - " +
            "C12 F13 B8 B12 C8 C13 A10 D10 A11 D11 B7 D12 C7 E12 A5 D9 - - " +
            "A6 E9 A3 B5 A4 B6 B1 C2 B2 D2"),
-    ("J2p", "D1 E1 E11 F11"), # top to bottom, starting with 57
+    ("J2p", "- D1 E1 E11 F11"), # top to bottom, starting with 57
 
-    ("J3", "AB27 F8 AA26 F9 B3 G8 C3 H8 D4 H7 - - " +
+    ("J3", "- AB27 F8 AA26 F9 B3 G8 C3 H8 D4 H7 - - " +
            "E4 J7 E2 K8 E3 K7 E6 J9 E7 J10 C4 J12 D5 G10 C5 J12 - - " +
            "D6 K12 F6 G11 G7 G12 D7 A8 E8 A9"),
-    ("J3p", "C9 C10 H12 H13"), # top to bottom, starting with 117
+    ("J3p", "- C9 C10 H12 H13"), # top to bottom, starting with 117
 
-    ("J4", "- - AD3 AE1 AD4 AE2 - - AB3 AC1 - - " +
+    ("J4", "- - - AD3 AE1 AD4 AE2 - - AB3 AC1 - - " +
            "AB4 AC2 - - Y3 AA1 Y4 AA2 - - V3 W1 V4 W2 - - - -" +
            "T3 U1 T4 R1 - R2 P3 U2 P4 -"),
-    ("J4p", "M3 M4 - H3 H4 J14 AD29 - N1 N2 - J1 J2") # top to bottom, starting with 169
+    ("J4p", "- M3 M4 - H3 H4 J14 AD29 - N1 N2 - J1 J2") # top to bottom, starting with 169
 ]
 
 # Platform -----------------------------------------------------------------------------------------

litex_boards/platforms/de10nano.py

@@ -171,7 +171,7 @@ class Platform(AlteraPlatform):
         self.add_extension(_mister_sdram_module_io)
 
     def create_programmer(self):
-        return USBBlaster()
+        return USBBlaster(cable_name="DE-SoC", device_id=2)
 
     def do_finalize(self, fragment):
         AlteraPlatform.do_finalize(self, fragment)

litex_boards/platforms/sds1104xe.py

@@ -71,31 +71,31 @@ _io = [ # Documented by https://github.com/360nosc0pe project.
         Subsignal("a", Pins(
             "J21 K18 J18 R16 P16 T18 R18 T19",
             "R19 P18 P17 P15 N15"),
-            IOStandard("SSTL135")),
+            IOStandard("SSTL15")),
-        Subsignal("ba",    Pins("K21 J20 J22"), IOStandard("SSTL135")),
+        Subsignal("ba",    Pins("K21 J20 J22"), IOStandard("SSTL15")),
-        Subsignal("ras_n", Pins("L21"), IOStandard("SSTL135")),
+        Subsignal("ras_n", Pins("L21"), IOStandard("SSTL15")),
-        Subsignal("cas_n", Pins("L22"), IOStandard("SSTL135")),
+        Subsignal("cas_n", Pins("L22"), IOStandard("SSTL15")),
-        Subsignal("we_n",  Pins("K19"), IOStandard("SSTL135")),
+        Subsignal("we_n",  Pins("K19"), IOStandard("SSTL15")),
-        #Subsignal("cs_n", Pins(""), IOStandard("SSTL135")), # Pulled low.
+        #Subsignal("cs_n", Pins(""), IOStandard("SSTL15")), # Pulled low.
-        #Subsignal("dm",   Pins(""), IOStandard("SSTL135")), # Pulled low.
+        #Subsignal("dm",   Pins(""), IOStandard("SSTL15")), # Pulled low.
         Subsignal("dq", Pins(
             " T21  U21  T22  U22  W20  W21 U20   V20",
             "AA22 AB22 AA21 AB21 AB19 AB20 Y19  AA19",
 	        " W16  Y16  U17  V17 AA17 AB17 AA16 AB16",
 	        " V14  V13  W13  Y14 AA14  Y13 AA13 AB14"),
-            IOStandard("SSTL135"),
+            IOStandard("SSTL15"),
             Misc("IN_TERM=UNTUNED_SPLIT_40")),
         Subsignal("dqs_p", Pins("V22 Y20 U15 W15"),
-            IOStandard("DIFF_SSTL135"),
+            IOStandard("DIFF_SSTL15"),
             Misc("IN_TERM=UNTUNED_SPLIT_40")),
         Subsignal("dqs_n", Pins("W22 Y21 U16 Y15"),
-            IOStandard("DIFF_SSTL135"),
+            IOStandard("DIFF_SSTL15"),
             Misc("IN_TERM=UNTUNED_SPLIT_40")),
-        Subsignal("clk_p",   Pins("T16"), IOStandard("DIFF_SSTL135")),
+        Subsignal("clk_p",   Pins("T16"), IOStandard("DIFF_SSTL15")),
-        Subsignal("clk_n",   Pins("T17"), IOStandard("DIFF_SSTL135")),
+        Subsignal("clk_n",   Pins("T17"), IOStandard("DIFF_SSTL15")),
-        Subsignal("cke",     Pins("M21"), IOStandard("SSTL135")),
+        Subsignal("cke",     Pins("M21"), IOStandard("SSTL15")),
-        Subsignal("odt",     Pins("M22"), IOStandard("SSTL135")),
+        Subsignal("odt",     Pins("M22"), IOStandard("SSTL15")),
-        Subsignal("reset_n", Pins("V18"), IOStandard("SSTL135")),
+        Subsignal("reset_n", Pins("V18"), IOStandard("SSTL15")),
         Misc("SLEW=FAST"),
     ),
 ]
@@ -109,6 +109,8 @@ _connectors = []
 class Platform(XilinxPlatform):
     def __init__(self):
         XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io,  _connectors, toolchain="vivado")
+        self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 33]")
+        self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
 
     def create_programmer(self):
         return VivadoProgrammer()

litex_boards/targets/arrow_sockit.py

@@ -28,6 +28,7 @@ from litex.soc.integration.soc_sdram import soc_sdram_argdict, soc_sdram_args
 from litex.soc.cores.led             import LedChaser
 
 from litex.build.io import DDROutput
+from litex.build.generic_platform  import Pins, IOStandard, Subsignal
 
 from litex_boards.platforms import arrow_sockit
 
@@ -160,14 +161,14 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    parser = argparse.ArgumentParser(description="LiteX SoC on SoCKit")
+    parser = argparse.ArgumentParser(description="LiteX SoC on the Arrow/Terasic SoCKit")
     parser.add_argument("--single-rate-sdram",   action="store_true", help="clock SDRAM with 1x the sytem clock (instead of 2x)")
     parser.add_argument("--mister-sdram-xs-v22", action="store_true", help="Use optional MiSTer SDRAM module XS v2.2 on J2 on GPIO daughter card")
     parser.add_argument("--mister-sdram-xs-v24", action="store_true", help="Use optional MiSTer SDRAM module XS v2.4 on J2 on GPIO daughter card")
     parser.add_argument("--build",               action="store_true", help="Build bitstream")
     parser.add_argument("--load",                action="store_true", help="Load bitstream")
     parser.add_argument("--revision",            default="revd",      help="Board revision: revb (default), revc or revd")
-    parser.add_argument("--sys-clk-freq",        default=50e6,       help="System clock frequency (default: 50MHz)")
+    parser.add_argument("--sys-clk-freq",        default=50e6,        help="System clock frequency (default: 50MHz)")
     builder_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()

litex_boards/targets/sds1104xe.py

@@ -61,11 +61,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_etherbone=False, eth_ip="192.168.1.50", **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), with_etherbone=True, eth_ip="192.168.1.50", **kwargs):
         platform = sds1104xe.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
-        if kwargs["uart_name"] == "serial":
+        if kwargs.get("uart_name", "serial") == "serial":
             kwargs["uart_name"] = "crossover" # Defaults to Crossover UART.
         SoCCore.__init__(self, platform, sys_clk_freq,
             ident          = "LiteX SoC on Siglent SDS1104X-E",