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Merge pull request #278 from mmicko/efinix_t20 

Initial support for Efinix Trion T20 BGA256 Dev Kit
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enjoy-digital 2021-10-15 15:37:33 +02:00 committed by GitHub
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80
litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py Normal file
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#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 Miodrag Milanovic <mmicko@gmail.com>
# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.efinix.platform import EfinixPlatform
from litex.build.efinix import EfinixProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk
("clk50", 0, Pins("L13"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
# Leds
("user_led", 0, Pins("D14"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
("user_led", 1, Pins("E13"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
("user_led", 2, Pins("G13"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
("user_led", 3, Pins("F14"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
("user_led", 4, Pins("N14"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
("user_led", 5, Pins("N16"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
("user_led", 6, Pins("P15"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
("user_led", 7, Pins("M14"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
# Buttons
("user_btn", 0, Pins("P2"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
("user_btn", 1, Pins("N3"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
("user_btn", 2, Pins("L4"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
# Switches
("user_sw", 0, Pins("H14"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
("user_sw", 1, Pins("H15"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
("user_sw", 2, Pins("H16"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("P3")),
Subsignal("clk", Pins("M3")),
Subsignal("mosi", Pins("L3")),
Subsignal("miso", Pins("N1")),
IOStandard("3.3_V_LVTTL_/_LVCMOS")
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
["H4", # - - 26 25 24 23 22 21 20 19 18 16 15 14 13 12 11
" - - H4 H2 H3 L1 H1 H5 J2 K2 K1 J3 K3 J4 L2 K4 J5",
# - 27 28 29 30 31 32 33 34 35 36 37 39 40 41 42 43
" - G3 G5 G2 F1 G1 F2 C1 E2 F3 D1 E1 E3 F5 C2 G4 F4"],
["H2", # - 45 47 49 51 53 55 57 59 61 - 63 65 67 69 71 73
" - B2 D4 D5 C4 B4 E4 A3 A4 B5 - B7 A6 C5 D7 B8 D8",
# - 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74
" - B1 D3 C3 A2 B3 D6 E6 C6 E5 A7 B6 A8 E7 C7 C8 D9"],
["H3", #158 155 153 150 127 124 122 120 117 111 105 81 79 77
"L12 P15 N14 L14 G14 G15 F15 E15 G13 F12 E13 C10 A10 D10",
#156 154 151 149 126 123 121 118 113 110 104 - 78 76
"M14 N16 K13 R16 G16 F16 G12 F14 F13 E14 D14 - A9 C9"],
]
# Platform -----------------------------------------------------------------------------------------
class Platform(EfinixPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
EfinixPlatform.__init__(self, "T20F256", _io, _connectors, toolchain="efinity")
def create_programmer(self):
return EfinixProgrammer()
def do_finalize(self, fragment):
EfinixPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)

107
litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py Executable file
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#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 Miodrag Milanovic <mmicko@gmail.com>
# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import efinix_trion_t20_bga256_dev_kit
from litex.build.generic_platform import *
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
# # #
clk50 = platform.request("clk50")
rst_n = platform.request("user_btn", 0)
# PLL
self.submodules.pll = pll = TRIONPLL(platform)
self.comb += pll.reset.eq(~rst_n)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
# Default peripherals
serial = [
("serial", 0,
Subsignal("tx", Pins("H4:18")), # 27 on H4
Subsignal("rx", Pins("H4:19")), # 28 on H4
IOStandard("3.3_V_LVTTL_/_LVCMOS") , Misc("WEAK_PULLUP")
)
]
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), with_spi_flash=False, with_led_chaser=True, **kwargs):
platform = efinix_trion_t20_bga256_dev_kit.Platform()
platform.add_extension(serial)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
#ident = "LiteX SoC on Efinix Trion T20 BGA256 Dev Kit", # FIXME: Crash design.
#ident_version = True,
integrated_rom_no_we = True, # FIXME: Avoid this.
integrated_sram_no_we = True, # FIXME: Avoid this.
integrated_main_ram_no_we = True, # FIXME: Avoid this.
**kwargs
)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import W25Q32JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="1x", module=W25Q32JV(Codes.READ_1_1_1), with_master=True)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_spi_flash = args.with_spi_flash,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, f"outflow/{soc.build_name}.bit"))
if __name__ == "__main__":
main()

2
test/test_targets.py
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@ -18,11 +18,13 @@ class TestTargets(unittest.TestCase):
"qmtech_daughterboard", # Reason: Not a real platform.
"quicklogic_quickfeather", # Reason: No default clock.
"efinix_trion_t120_bga576_dev_kit", # Reason: Require Efinity toolchain.
"efinix_trion_t20_bga256_dev_kit", # Reason: Require Efinity toolchain.
]
excluded_targets = [
"simple", # Reason: Generic target.
"quicklogic_quickfeather", # Reason: No default clock.
"efinix_trion_t120_bga576_dev_kit", # Reason: Require Efinity toolchain.
"efinix_trion_t20_bga256_dev_kit", # Reason: Require Efinity toolchain.
]
# Build simple design for all platforms.