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targets/siglent_sds1104xe: Review.

This commit is contained in:
Florent Kermarrec 2023-10-23 19:25:12 +02:00
parent 71d8b17fff
commit 0d560bc240
1 changed files with 2 additions and 1 deletions
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3
litex_boards/targets/siglent_sds1104xe.py
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@ -104,6 +104,7 @@ class BaseSoC(SoCCore):
clock_pads = self.platform.request("eth_clocks"), clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth")) pads = self.platform.request("eth"))
# Etherbone.
self.add_etherbone( self.add_etherbone(
phy = self.ethphy, phy = self.ethphy,
ip_address = "192.168.1.51", ip_address = "192.168.1.51",
@ -112,7 +113,7 @@ class BaseSoC(SoCCore):
interface = "hybrid", interface = "hybrid",
endianness = self.cpu.endianness) endianness = self.cpu.endianness)
## Software Interface. # Software Interface.
ethmac = self.get_module("ethcore_etherbone").mac ethmac = self.get_module("ethcore_etherbone").mac
ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant
ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False) ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False)