targets/ulx3s: revert to cl=2

2019-09-25 13:58:45 +02:00 · 2019-09-25 13:58:45 +02:00 · 0ead12bae8
parent e94c6c8f27
commit 0ead12bae8
1 changed files with 1 additions and 1 deletions
--- a/litex_boards/partner/targets/ulx3s.py
+++ b/litex_boards/partner/targets/ulx3s.py
@ -63,7 +63,7 @@ class BaseSoC(SoCSDRAM):
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        if not self.integrated_main_ram_size:
-            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=3)
+            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2)
            sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
            self.register_sdram(self.sdrphy,
                                sdram_module.geom_settings,