Merge pull request #587 from akioolin/master
Add HSEDA XC7A35T board support
This commit is contained in:
enjoy-digital
GitHub
commit
1013a53240
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2024 Akio Lin <akioolin@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# CPU Clock
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("clk50", 0, Pins("D4"), IOStandard("LVCMOS33")),
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# CPU Reset
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("cpu_reset", 0, Pins("C4"), IOStandard("LVCMOS33")),
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# User LEDs
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("user_led", 0, Pins("K12"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("L14"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("L13"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("M14"), IOStandard("LVCMOS33")),
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# User Keys
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("user_btn", 0, Pins("D11"), IOStandard("SSTL15")),
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("user_btn", 1, Pins("G11"), IOStandard("SSTL15")),
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("user_btn", 2, Pins("H11"), IOStandard("SSTL15")),
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("user_btn", 3, Pins("K13"), IOStandard("LVCMOS33")),
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# UART
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("serial", 0,
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Subsignal("tx", Pins("E6")),
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Subsignal("rx", Pins("C7")),
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IOStandard("LVCMOS33")
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),
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# I2C bus for RTC DS1302
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("i2c", 0,
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Subsignal("sda", Pins("N13"), IOStandard("LVCMOS33")),
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Subsignal("scl", Pins("M12"), IOStandard("LVCMOS33")),
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),
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# RST for RTC DS1302
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("gpio", 0, Pins("P13"), IOStandard("LVCMOS33")),
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# SD-Card.
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("sdcard", 0,
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# Subsignal("cd", Pins("N6")),
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Subsignal("cmd", Pins("M4")),
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Subsignal("clk", Pins("N4")),
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Subsignal("data", Pins("P3 P4 N3 M5")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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# SPIFlash
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# N25Q128A13ESE40F
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("spiflash", 0,
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Subsignal("cs_n", Pins("L12")),
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Subsignal("clk", Pins("E8")),
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Subsignal("mosi", Pins("J13")),
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Subsignal("miso", Pins("J14")),
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Subsignal("wp", Pins("K15")),
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Subsignal("hold", Pins("K16")),
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IOStandard("LVCMOS33"),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("L12")),
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Subsignal("clk", Pins("E8")),
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Subsignal("dq", Pins("J13", "J14", "K15", "K16")),
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IOStandard("LVCMOS33")
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),
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# DDR3 SDRAM
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# MT41K128M16JT-125
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("ddram", 0,
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Subsignal("a", Pins("C11 A12 D9 A15 B12 C9 B11 D8 B10 C8 C12 A9 B14 A8"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("C14 A13 B15"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("C16"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("D13"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("B16"), IOStandard("SSTL15")),
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# cs_n is hardwired on the board
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#Subsignal("cs_n", Pins("-"), IOStandard("SSTL135")),
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Subsignal("dm", Pins("F12 G16"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"F15 F13 E15 E13 D16 E11 E16 E12",
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"H13 H16 G15 H14 H12 J15 G12 J16"),
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IOStandard("SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("D14 G14"),
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IOStandard("DIFF_SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_n", Pins("D15 F14"),
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IOStandard("DIFF_SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("clk_p", Pins("B9"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("A10"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("A14"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("C13"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("D10"), IOStandard("LVCMOS15")),
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Misc("SLEW=FAST"),
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),
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]
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# On board J6, J7
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_connectors = [
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("J6", {
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#odd row even row
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2: "M16",
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3: "N16", 4: "L15",
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6: "M15",
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7: "R16", 8: "P16",
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9: "R15", 10: "P15",
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11: "T15", 12: "P14",
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13: "T14", 14: "N14",
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15: "N12", 16: "T13",
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17: "N11", 18: "R13",
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19: "R11", 20: "T12",
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21: "R10", 22: "R12",
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23: "T10", 24: "P11",
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25: "T9", 26: "P10",
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27: "T8", 28: "P9",
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29: "T7", 30: "N9",
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31: "R7", 32: "R8",
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33: "R6", 34: "P8",
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35: "T5", 36: "N6",
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37: "R5", 38: "M6",
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39: "P6",
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}),
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("J7", {
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#odd row even row
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2: "K3",
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3: "J3", 4: "J4",
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6: "J5",
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7: "H4", 8: "G4",
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9: "H5", 10: "G5",
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11: "G1", 12: "F3",
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13: "G2", 14: "F4",
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15: "F2", 16: "C2",
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17: "E1", 18: "C3",
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19: "E2", 20: "D3",
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21: "D1", 22: "E3",
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23: "C1", 24: "A4",
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25: "B1", 26: "A5",
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27: "B2", 28: "E5",
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29: "A2", 30: "F5",
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31: "A3", 32: "D5",
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33: "B4", 34: "D6",
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35: "B5", 36: "A7",
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37: "B6", 38: "B7",
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39: "C6",
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})
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, toolchain="vivado", with_core_resources=True):
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device = "xc7a35tftg256-1"
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io = _io
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connectors = _connectors
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Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 15]")
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self.add_platform_command("set_property CFGBVS VCCO [current_design]")
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self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
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def create_programmer(self):
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bscan_spi = "bscan_spi_xc7a35t.bit"
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return OpenOCD("openocd_xc7_ft232.cfg", bscan_spi)
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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@ -0,0 +1,132 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2024 Akio Lin <akioolin@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# http://www.hseda.com/product/xilinx/XC7A35T/XC7A35T.htm
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import hseda_xc7a35t
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41K128M16
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from litedram.phy import s7ddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_dqs = ClockDomain()
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self.cd_idelay = ClockDomain()
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# # #
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self.pll = pll = S7PLL(speedgrade=-1)
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try:
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reset_button = platform.request("cpu_reset")
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self.comb += pll.reset.eq(~reset_button | self.rst)
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except:
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("clk50"), 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, toolchain="vivado", sys_clk_freq=100e6,
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with_led_chaser = True,
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with_spi_flash = False,
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with_sdcard = True,
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**kwargs):
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platform = hseda_xc7a35t.Platform(toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on HSEDA XC7A35T", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K128M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import N25Q128A13
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", module=N25Q128A13(Codes.READ_1_1_4), rate="1:1", with_master=True)
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# SD Card ----------------------------------------------------------------------------------
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if with_sdcard:
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self.add_sdcard()
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=hseda_xc7a35t.Platform, description="LiteX SoC on HSEDA XC7A35T.")
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parser.add_target_argument("--flash", action="store_true", help="Write FPGA bitstream into spi flash.")
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parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash support.")
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args = parser.parse_args()
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soc = BaseSoC(
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toolchain = args.toolchain,
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sys_clk_freq = args.sys_clk_freq,
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with_spi_flash = args.with_spi_flash,
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with_sdcard = args.with_sdcard,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, builder.get_bitstream_filename(mode="flash"))
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if __name__ == "__main__":
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main()
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