targets/de10lite: minor cleanup on import/_CRG

This commit is contained in:
Florent Kermarrec 2019-12-31 17:26:09 +01:00
parent 9d6a6c1bcb
commit 10e5248bda
1 changed files with 8 additions and 8 deletions

View File

@ -15,17 +15,17 @@ from litex.soc.integration.soc_core import mem_decoder
from litedram.modules import IS42S16320 from litedram.modules import IS42S16320
from litedram.phy import GENSDRPHY from litedram.phy import GENSDRPHY
from litevideo.terminal.core import Terminal
from litevideo.terminal.core import Terminal
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(Module): class _CRG(Module):
def __init__(self, platform): def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_vga = ClockDomain(reset_less=True)
self.clock_domains.cd_sys_ps = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True) self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_vga = ClockDomain(reset_less=True)
# # # # # #
@ -41,13 +41,8 @@ class _CRG(Module):
self.cd_sys_ps.rst.eq(~rst_n) self.cd_sys_ps.rst.eq(~rst_n)
] ]
# sys clk / sdram clk from PLL # sys clk / sdram clk / vga_clk from PLL
pll_clk_out = Signal(6) pll_clk_out = Signal(6)
self.comb += self.cd_sys.clk.eq(pll_clk_out[0])
self.comb += self.cd_sys_ps.clk.eq(pll_clk_out[1])
self.comb += self.cd_vga.clk.eq(pll_clk_out[2])
self.specials += \ self.specials += \
Instance("ALTPLL", Instance("ALTPLL",
p_BANDWIDTH_TYPE = "AUTO", p_BANDWIDTH_TYPE = "AUTO",
@ -77,6 +72,11 @@ class _CRG(Module):
i_PFDENA = 1, i_PFDENA = 1,
i_PLLENA = 1, i_PLLENA = 1,
) )
self.comb += [
self.cd_sys.clk.eq(pll_clk_out[0]),
self.cd_sys_ps.clk.eq(pll_clk_out[1]),
self.cd_vga.clk.eq(pll_clk_out[2])
]
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------