add Alientek DaVinci Pro FPGA board
This commit is contained in:
Hans Baier
parent
aaab2dcfe2
commit
110c051779
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# Board product page: https://www.alientek.com/productinfo/945752.html
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# Taobao item: https://item.taobao.com/item.htm?id=641238123452
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# The Taobao agent I used: https://www.basetao.com/?ejATJf+gGuEbpa8IBg
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk50", 0, Pins("R4"), IOStandard("SSTL135")),
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("cpu_reset", 0, Pins("U7"), IOStandard("SSTL135")),
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# Leds
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("user_led", 0, Pins("V9"), IOStandard("SSTL135")),
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("user_led", 1, Pins("Y8"), IOStandard("SSTL135")),
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("user_led", 2, Pins("Y7"), IOStandard("SSTL135")),
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("user_led", 3, Pins("W7"), IOStandard("SSTL135")),
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# Buttons
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("user_btn", 0, Pins("T4"), IOStandard("SSTL135")),
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("user_btn", 1, Pins("T3"), IOStandard("SSTL135")),
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("user_btn", 2, Pins("R6"), IOStandard("SSTL135")),
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("user_btn", 3, Pins("T6"), IOStandard("SSTL135")),
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# Beeper
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("beeper", 3, Pins("V7"), IOStandard("SSTL135")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("D17")),
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Subsignal("rx", Pins("E14")),
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IOStandard("LVCMOS33"),
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),
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# RS485
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("rs485", 0,
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Subsignal("tx", Pins("T18")),
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Subsignal("rx", Pins("R18")),
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IOStandard("LVCMOS33"),
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),
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# CAN bus
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("can", 0,
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Subsignal("tx", Pins("TR18")),
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Subsignal("rx", Pins("AA19")),
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IOStandard("LVCMOS33"),
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),
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# EEPROM + RTC
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("i2c", 0,
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Subsignal("sda", Pins("A19")),
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Subsignal("scl", Pins("F13")),
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IOStandard("LVCMOS33")
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),
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# USB FIFO
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("usb_clk", 0, Pins("E19"), IOStandard("LVCMOS33")),
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("usb_fifo", 0, # Can be used when FT232H's Channel is configured to ASYNC FIFO 245 mode
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Subsignal("data", Pins("C17 F15 F18 E18 E21 D21 F21 E22")),
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Subsignal("rxf_n", Pins("F16")),
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Subsignal("txe_n", Pins("E17")),
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Subsignal("rd_n", Pins("F19")),
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Subsignal("wr_n", Pins("F20")),
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Subsignal("siwua", Pins("G21")),
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Subsignal("oe_n", Pins("D19")),
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Misc("SLEW=FAST"),
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Drive(8),
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IOStandard("LVCMOS33"),
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),
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# SDCard
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("spisdcard", 0,
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Subsignal("cd", Pins("A18")),
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Subsignal("clk", Pins("A16")),
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Subsignal("mosi", Pins("A15")),
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Subsignal("cs_n", Pins("A14")),
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Subsignal("miso", Pins("B17")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("data", Pins("B17 B18 A13 A14"),),
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Subsignal("cmd", Pins("A15"),),
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Subsignal("clk", Pins("A16")),
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Subsignal("cd", Pins("A18")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"AA4 AB2 AA5 AB5 AB1 U3 W1 T1", # A0-A7
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"V2 U2 Y1 W2 Y2 U1 V3"), # A8-A14
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("AA3 Y3 Y4"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("V4"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("W4"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("AA1"), IOStandard("SSTL135")),
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Subsignal("cs_n", Pins("AB3"), IOStandard("SSTL135")),
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Subsignal("dm", Pins("D2 G2 M2 M5"), IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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"C2 G1 A1 F3 F1 B2 B1 E2 H3 G3 H2 H5 J1 J5 K1 H4", # D0-D15
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"L4 M3 L3 J6 K3 K6 J4 L5 P1 N4 R1 N2 M6 N5 P6 P2"), # D16-D31
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IOStandard("SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("dqs_p", Pins("E1 K2 M1 P5"), IOStandard("DIFF_SSTL135")),
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Subsignal("dqs_n", Pins("D1 J2 L1 P4"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("T5"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("U5"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("W6"), IOStandard("SSTL135")),
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Misc("SLEW=FAST"),
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),
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# RGMII Ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("V18")),
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Subsignal("rx", Pins("U20")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("N20")),
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Subsignal("mdio", Pins("N22")),
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Subsignal("mdc", Pins("M22")),
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Subsignal("rx_ctl", Pins("AA20")),
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Subsignal("rx_data", Pins("AA21 V20 U22 V22")),
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Subsignal("tx_ctl", Pins("V19")),
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Subsignal("tx_data", Pins("T21 U21 P19 R19")),
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IOStandard("LVCMOS33")
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),
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("eth_clocks", 1,
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Subsignal("tx", Pins("W19")),
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Subsignal("rx", Pins("Y18")),
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IOStandard("LVCMOS33")
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),
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("eth", 1,
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Subsignal("rst_n", Pins("N20")),
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Subsignal("mdio", Pins("N22")),
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Subsignal("mdc", Pins("M20")),
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Subsignal("rx_ctl", Pins("AA20")),
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Subsignal("rx_data", Pins("AA21 V20 U22 V22")),
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Subsignal("tx_ctl", Pins("V19")),
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Subsignal("tx_data", Pins("T21 U21 P19 R19")),
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IOStandard("LVCMOS33")
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),
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# HDMI I2C
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("i2c", 1,
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Subsignal("sda", Pins("N18")),
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Subsignal("scl", Pins("L21")),
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IOStandard("LVCMOS33")
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),
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# HDMI In
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("adv7611", 0,
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Subsignal("clk", Pins("L19")),
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Subsignal("rst_n", Pins("N19")),
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Subsignal("hsync_n", Pins("M22")),
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Subsignal("vsync_n", Pins("M15")),
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Subsignal("de_n", Pins("M21")),
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Subsignal("r", Pins("M16 L16 K16 K18 K19 M13 L13 L14")), # D16-D23
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Subsignal("g", Pins("L15 K13 K14 J16 J15 H15 J14 H14")), # D8-D15
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Subsignal("b", Pins("H13 G13 J19 H19 G16 G15 G18 G17")), # D0-D7
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IOStandard("LVCMOS33")
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),
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# HDMI Out
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("hdmi_out", 0,
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Subsignal("clk_p", Pins("J20"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("J21"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("J22"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("H22"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("K21"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("K22"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("H20"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("G20"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("AA8"), IOStandard("SSTL135")),
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Subsignal("sda", Pins("AB8"), IOStandard("SSTL135")),
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),
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# RGB TFT-LCD
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("tft_lcd", 0,
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Subsignal("d", Pins("L14 L13 M13 K19 K18 K16 L16 M16", # D0-D7
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"H14 J14 H15 J15 J16 K14 K13 L15", # D8-D15
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"G17 G18 G15 G16 H19 J19 G13 H13" # G16-D23
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), IOStandard("LVCMOS33")),
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Subsignal("hsync_n", Pins("M22"), IOStandard("LVCMOS33")),
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Subsignal("vsync_n", Pins("M15"), IOStandard("LVCMOS33")),
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Subsignal("de_n", Pins("M21"), IOStandard("LVCMOS33")),
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Subsignal("bl", Pins("W9"), IOStandard("SSTL135")),
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Subsignal("pclk", Pins("H17"), IOStandard("LVCMOS33")),
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Subsignal("rst", Pins("Y9"), IOStandard("SSTL135")),
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),
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# SFP
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("gtp_refclk", 0,
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Subsignal("p", Pins("F10")),
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Subsignal("n", Pins("E10"))
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),
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("sfp_tx", 0,
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Subsignal("p", Pins("B4")),
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Subsignal("n", Pins("A4"))
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),
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("sfp_rx", 0,
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Subsignal("p", Pins("B8")),
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Subsignal("n", Pins("A8"))
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),
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("sfp_tx_disable_n", 0, Pins("V5"), IOStandard("SSTL135")),
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("sfp_rx_los", 0, Pins("U6"), IOStandard("SSTL135")),
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# SFP1
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("sfp_tx", 1,
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Subsignal("p", Pins("D5")),
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Subsignal("n", Pins("C5")),
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),
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("sfp_rx", 1,
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Subsignal("p", Pins("D11")),
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Subsignal("n", Pins("C11")),
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),
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("sfp_tx_disable_n", 1, Pins("Y6"), IOStandard("SSTL135")),
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("sfp_rx_los", 1, Pins("AA6"), IOStandard("SSTL135")),
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("N15"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("F6")),
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Subsignal("clk_n", Pins("E6")),
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Subsignal("rx_p", Pins("D9")),
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Subsignal("rx_n", Pins("C9")),
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Subsignal("tx_p", Pins("D7")),
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Subsignal("tx_n", Pins("C7"))
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),
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("pcie_x2", 0,
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Subsignal("rst_n", Pins("N15"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("F6")),
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Subsignal("clk_n", Pins("E6")),
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Subsignal("rx_p", Pins("D9 B10")),
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Subsignal("rx_n", Pins("C9 A10")),
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Subsignal("tx_p", Pins("D7 B6")),
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Subsignal("tx_n", Pins("C7 A6"))
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("J3", {
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1: "N14", 2: "N13",
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3: "R14", 4: "P14",
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5: "P17", 6: "N17",
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7: "R16", 8: "P15",
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9: "P16", 10: "R17",
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11: "W17", 12: "V17",
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13: "U18", 14: "U17",
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15: "AB18", 16: "AA18",
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17: "C13", 18: "B13",
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19: "C14", 20: "C15",
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21: "B15", 22: "B16",
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23: "C18", 24: "C19",
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25: "B20", 26: "A20",
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27: "D20", 28: "C20",
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29: "B22", 30: "C22",
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31: "B21", 32: "A21",
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33: "D14", 34: "D15",
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35: "E16", 36: "D16",
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}),
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("J4", {
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1: "N15", 2: "Y17",
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3: "V10", 4: "W10",
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5: "AA9", 6: "AB10",
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7: "T14", 8: "T15",
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9: "V13", 10: "V14",
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11: "T16", 12: "U16",
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13: "Y14", 14: "W14",
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15: "U15", 16: "V15",
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17: "W16", 18: "W15",
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19: "Y11", 20: "Y12",
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21: "AA10", 22: "AA11",
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23: "AB11", 24: "AB12",
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25: "W11", 26: "W12",
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27: "AA13", 28: "AB13",
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29: "Y13", 30: "AA14",
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31: "AA15", 32: "AB15",
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33: "AB16", 34: "AB17",
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35: "Y16", 36: "AA16",
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}),
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]
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def raw_j3():
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return [("J3", 0, Pins(" ".join([f"J3:{i+1:d}" for i in range(36)])), IOStandard("LVCMOS33"))]
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def raw_j4():
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return [("J4", 0, Pins(" ".join([f"J4:{i+1:d}" for i in range(36)])), IOStandard("LVCMOS33"))]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, toolchain="vivado", variant="a7-35"):
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assert variant in ["a7-35", "a7-100"]
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kgates = variant.split("-")[-1]
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self.kgates = kgates
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Xilinx7SeriesPlatform.__init__(self, f"xc7a{kgates}t-fgg484-1", _io, _connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]",
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"set_property CFGBVS VCCO [current_design]",
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"set_property CONFIG_VOLTAGE 3.3 [current_design]",
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"set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]"
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]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 35]")
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def create_programmer(self):
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return OpenOCD("openocd_alientek_davincipro.cfg", f"bscan_spi_xc7a{self.kgates}t.bit")
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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try:
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self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
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except ConstraintError:
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pass
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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self.add_period_constraint(self.lookup_request("usb_clk", loose=True), 1e9/60e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6)
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@ -0,0 +1,274 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# Board product page: https://www.alientek.com/productinfo/945752.html
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# Taobao item: https://item.taobao.com/item.htm?id=641238123452
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# The Taobao agent I used: https://www.basetao.com/?ejATJf+gGuEbpa8IBg
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import alientek_davincipro
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.gpio import GPIOIn, GPIOTristate
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from litex.soc.cores.xadc import XADC
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from litex.soc.cores.dna import DNA
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from litex.soc.cores.video import VideoS7HDMIPHY
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from litedram.modules import IS43TR16128B
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from litedram.phy import s7ddrphy
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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from litepcie.phy.s7pciephy import S7PCIEPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_dram=True, with_rst=True, with_hdmi=False):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_eth = ClockDomain()
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if with_hdmi:
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self.cd_hdmi = ClockDomain()
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self.cd_hdmi5x = ClockDomain()
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if with_dram:
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self.cd_sys4x = ClockDomain()
|
||||
self.cd_sys4x_dqs = ClockDomain()
|
||||
self.cd_idelay = ClockDomain()
|
||||
|
||||
# # #
|
||||
|
||||
# Clk/Rst.
|
||||
clk50 = platform.request("clk50")
|
||||
rst = ~platform.request("cpu_reset") if with_rst else 0
|
||||
|
||||
# PLL.
|
||||
self.pll = pll = S7PLL(speedgrade=-1)
|
||||
self.comb += pll.reset.eq(rst | self.rst)
|
||||
pll.register_clkin(clk50, 50e6)
|
||||
pll.create_clkout(self.cd_sys, sys_clk_freq)
|
||||
pll.create_clkout(self.cd_eth, 25e6)
|
||||
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
|
||||
if with_dram:
|
||||
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
|
||||
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
|
||||
pll.create_clkout(self.cd_idelay, 200e6)
|
||||
|
||||
# IdelayCtrl.
|
||||
if with_dram:
|
||||
self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
|
||||
|
||||
if with_hdmi:
|
||||
self.submodules.pll2 = pll2 = S7MMCM(speedgrade=-1)
|
||||
self.comb += pll2.reset.eq(rst | self.rst)
|
||||
pll2.register_clkin(clk50, 50e6)
|
||||
pll2.create_clkout(self.cd_hdmi, 25e6, margin=0)
|
||||
pll2.create_clkout(self.cd_hdmi5x, 125e6, margin=0)
|
||||
|
||||
# BaseSoC ------------------------------------------------------------------------------------------
|
||||
|
||||
class BaseSoC(SoCCore):
|
||||
def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=100e6,
|
||||
with_xadc = False,
|
||||
with_dna = False,
|
||||
with_ethernet = False,
|
||||
with_etherbone = False,
|
||||
eth_phy = "rgmii",
|
||||
eth_ip = "192.168.1.50",
|
||||
remote_ip = None,
|
||||
eth_dynamic_ip = False,
|
||||
with_pcie = False,
|
||||
with_led_chaser = True,
|
||||
with_buttons = True,
|
||||
with_gpio = False,
|
||||
with_video_colorbars = False,
|
||||
with_video_framebuffer = False,
|
||||
with_video_terminal = False,
|
||||
**kwargs):
|
||||
platform = alientek_davincipro.Platform(variant=variant, toolchain=toolchain)
|
||||
|
||||
with_hdmi = with_video_colorbars or with_video_framebuffer or with_video_terminal
|
||||
|
||||
# CRG --------------------------------------------------------------------------------------
|
||||
with_dram = (kwargs.get("integrated_main_ram_size", 0) == 0)
|
||||
self.crg = _CRG(platform, sys_clk_freq, with_dram, with_rst=True, with_hdmi=with_hdmi)
|
||||
|
||||
# SoCCore ----------------------------------------------------------------------------------
|
||||
SoCCore.__init__(self, platform, sys_clk_freq, ident=f"LiteX SoC on Alientek DaVinci Pro ({variant}t)", **kwargs)
|
||||
|
||||
# XADC -------------------------------------------------------------------------------------
|
||||
if with_xadc:
|
||||
self.xadc = XADC()
|
||||
|
||||
# DNA --------------------------------------------------------------------------------------
|
||||
if with_dna:
|
||||
self.dna = DNA()
|
||||
self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
|
||||
|
||||
# DDR3 SDRAM -------------------------------------------------------------------------------
|
||||
if not self.integrated_main_ram_size:
|
||||
self.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
|
||||
memtype = "DDR3",
|
||||
nphases = 4,
|
||||
sys_clk_freq = sys_clk_freq)
|
||||
self.add_sdram("sdram",
|
||||
phy = self.ddrphy,
|
||||
module = IS43TR16128B(sys_clk_freq, "1:4"),
|
||||
l2_cache_size = kwargs.get("l2_size", 8192)
|
||||
)
|
||||
|
||||
# Ethernet ---------------------------------------------------------------------------------
|
||||
if with_ethernet or with_etherbone:
|
||||
# RGMII Ethernet PHY -------------------------------------------------------------------
|
||||
if eth_phy == "rgmii":
|
||||
# phy
|
||||
self.ethphy = LiteEthPHYRGMII(
|
||||
clock_pads = self.platform.request("eth_clocks"),
|
||||
pads = self.platform.request("eth"))
|
||||
|
||||
# 1000BaseX Ethernet PHY ---------------------------------------------------------------
|
||||
if eth_phy == "1000basex":
|
||||
# phy
|
||||
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0)
|
||||
qpll_settings = QPLLSettings(
|
||||
refclksel = 0b001,
|
||||
fbdiv = 4,
|
||||
fbdiv_45 = 5,
|
||||
refclk_div = 1)
|
||||
refclk125 = self.platform.request("gtp_refclk")
|
||||
refclk125_se = Signal()
|
||||
self.specials += \
|
||||
Instance("IBUFDS_GTE2",
|
||||
i_CEB = 0,
|
||||
i_I = refclk125.p,
|
||||
i_IB = refclk125.n,
|
||||
o_O = refclk125_se)
|
||||
qpll = QPLL(refclk125_se, qpll_settings)
|
||||
self.submodules += qpll
|
||||
self.ethphy = A7_1000BASEX(
|
||||
qpll_channel = qpll.channels[0],
|
||||
data_pads = self.platform.request("sfp", 0),
|
||||
sys_clk_freq = self.clk_freq)
|
||||
|
||||
if with_etherbone:
|
||||
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip, with_ethmac=with_ethernet)
|
||||
elif with_ethernet:
|
||||
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip, local_ip=eth_ip if not eth_dynamic_ip else None, remote_ip=remote_ip)
|
||||
|
||||
# PCIe -------------------------------------------------------------------------------------
|
||||
if with_pcie:
|
||||
self.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x2"),
|
||||
data_width = 64,
|
||||
bar0_size = 0x20000)
|
||||
self.add_pcie(phy=self.pcie_phy, ndmas=1)
|
||||
|
||||
# HDMI Options -----------------------------------------------------------------------------
|
||||
if with_hdmi:
|
||||
self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi")
|
||||
if with_video_colorbars:
|
||||
self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
|
||||
if with_video_terminal:
|
||||
self.add_video_terminal(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
|
||||
if with_video_framebuffer:
|
||||
self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
|
||||
|
||||
# Leds -------------------------------------------------------------------------------------
|
||||
if with_led_chaser:
|
||||
self.leds = LedChaser(
|
||||
pads = platform.request_all("user_led"),
|
||||
sys_clk_freq = sys_clk_freq,
|
||||
)
|
||||
|
||||
# Buttons ----------------------------------------------------------------------------------
|
||||
if with_buttons:
|
||||
self.buttons = GPIOIn(
|
||||
pads = platform.request_all("user_btn"),
|
||||
with_irq = self.irq.enabled
|
||||
)
|
||||
|
||||
# GPIOs ------------------------------------------------------------------------------------
|
||||
if with_gpio:
|
||||
platform.add_extension(alientek_davincipro.raw_j3())
|
||||
self.gpio = GPIOTristate(
|
||||
pads = platform.request("J3"),
|
||||
with_irq = self.irq.enabled
|
||||
)
|
||||
|
||||
# Build --------------------------------------------------------------------------------------------
|
||||
|
||||
def main():
|
||||
from litex.build.parser import LiteXArgumentParser
|
||||
parser = LiteXArgumentParser(platform=alientek_davincipro.Platform, decription="LiteX SoC on Alientek Davinci Pro.")
|
||||
parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
|
||||
parser.add_target_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).")
|
||||
parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
|
||||
parser.add_target_argument("--with-xadc", action="store_true", help="Enable 7-Series XADC.")
|
||||
parser.add_target_argument("--with-dna", action="store_true", help="Enable 7-Series DNA.")
|
||||
parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
|
||||
parser.add_target_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
|
||||
parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
|
||||
parser.add_target_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server.")
|
||||
parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
|
||||
parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
|
||||
viopts = parser.target_group.add_mutually_exclusive_group()
|
||||
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
|
||||
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
|
||||
viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).")
|
||||
sdopts = parser.target_group.add_mutually_exclusive_group()
|
||||
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
|
||||
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
|
||||
parser.add_target_argument("--with-gpio", action="store_true", help="Enable GPIOs through PMOD.") # FIXME: Temporary test.
|
||||
args = parser.parse_args()
|
||||
|
||||
assert not (args.with_etherbone and args.eth_dynamic_ip)
|
||||
|
||||
soc = BaseSoC(
|
||||
variant = args.variant,
|
||||
toolchain = args.toolchain,
|
||||
sys_clk_freq = args.sys_clk_freq,
|
||||
with_xadc = args.with_xadc,
|
||||
with_dna = args.with_dna,
|
||||
with_ethernet = args.with_ethernet,
|
||||
with_etherbone = args.with_etherbone,
|
||||
eth_ip = args.eth_ip,
|
||||
remote_ip = args.remote_ip,
|
||||
eth_dynamic_ip = args.eth_dynamic_ip,
|
||||
with_buttons = True,
|
||||
with_gpio = args.with_gpio,
|
||||
with_pcie = args.with_pcie,
|
||||
with_video_colorbars = args.with_video_colorbars,
|
||||
with_video_framebuffer = args.with_video_framebuffer,
|
||||
with_video_terminal = args.with_video_terminal,
|
||||
**parser.soc_argdict
|
||||
)
|
||||
if args.with_spi_sdcard:
|
||||
soc.add_spi_sdcard()
|
||||
if args.with_sdcard:
|
||||
soc.add_sdcard()
|
||||
|
||||
builder = Builder(soc, **parser.builder_argdict)
|
||||
if args.build:
|
||||
builder.build(**parser.toolchain_argdict)
|
||||
|
||||
if args.load:
|
||||
prog = soc.platform.create_programmer()
|
||||
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
|
||||
|
||||
if args.flash:
|
||||
prog = soc.platform.create_programmer()
|
||||
prog.flash(0, builder.get_bitstream_filename(mode="flash"))
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue