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platforms/xilinx_zcu106.py: added connectors and FMC HPC0/1

This commit is contained in:
Gwenhael Goavec-Merou 2024-05-17 12:16:33 +02:00
parent c660a7a1af
commit 11956b1709
1 changed files with 159 additions and 1 deletions
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160
litex_boards/platforms/xilinx_zcu106.py
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@ -117,6 +117,164 @@ _io = [
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("FMC_HPC0", {
"CLK0_M2C_N" : "E14",
"CLK0_M2C_P" : "E15",
"CLK1_M2C_N" : "F10",
"CLK1_M2C_P" : "G10",
"DP0_C2M_N" : "R5",
"DP0_C2M_P" : "R6",
"DP0_M2C_N" : "R1",
"DP0_M2C_P" : "R2",
"DP1_C2M_N" : "T3",
"DP1_C2M_P" : "T4",
"DP1_M2C_N" : "U1",
"DP1_M2C_P" : "U2",
"DP2_C2M_N" : "N5",
"DP2_C2M_P" : "N6",
"DP2_M2C_N" : "P3",
"DP2_M2C_P" : "P4",
"DP3_C2M_N" : "U5",
"DP3_C2M_P" : "U6",
"DP3_M2C_N" : "V3",
"DP3_M2C_P" : "V4",
"DP4_C2M_N" : "M5",
"DP4_C2M_P" : "M6",
"DP4_M2C_N" : "L3",
"DP4_M2C_P" : "L4",
"DP5_C2M_N" : "L5",
"DP5_C2M_P" : "L6",
"DP5_M2C_N" : "L1",
"DP5_M2C_P" : "L2",
"DP6_C2M_N" : "M3",
"DP6_C2M_P" : "M4",
"DP6_M2C_N" : "N1",
"DP6_M2C_P" : "N2",
"DP7_C2M_N" : "K3",
"DP7_C2M_P" : "K4",
"DP7_M2C_N" : "J1",
"DP7_M2C_P" : "J2",
"GBTCLK0_M2C_C_N" : "V7",
"GBTCLK0_M2C_C_P" : "V8",
"GBTCLK1_M2C_C_N" : "77",
"GBTCLK1_M2C_C_P" : "T8",
"LA00_CC_N" : "F16",
"LA00_CC_P" : "F17",
"LA01_CC_N" : "H17",
"LA01_CC_P" : "H18",
"LA02_N" : "K20",
"LA02_P" : "L20",
"LA03_N" : "K18",
"LA03_P" : "K19",
"LA04_N" : "L16",
"LA04_P" : "L17",
"LA05_N" : "J17",
"LA05_P" : "K17",
"LA06_N" : "G19",
"LA06_P" : "H19",
"LA07_N" : "J15",
"LA07_P" : "J16",
"LA08_N" : "E17",
"LA08_P" : "E18",
"LA09_N" : "G16",
"LA09_P" : "H16",
"LA10_N" : "K15",
"LA10_P" : "L15",
"LA11_N" : "A12",
"LA11_P" : "A13",
"LA12_N" : "F18",
"LA12_P" : "G18",
"LA13_N" : "F15",
"LA13_P" : "G15",
"LA14_N" : "C12",
"LA14_P" : "C13",
"LA15_N" : "C16",
"LA15_P" : "D16",
"LA16_N" : "C17",
"LA16_P" : "D17",
"LA17_CC_N" : "E10",
"LA17_CC_P" : "F11",
"LA18_CC_N" : "D10",
"LA18_CC_P" : "D11",
"LA19_N" : "C11",
"LA19_P" : "D12",
"LA20_N" : "E12",
"LA20_P" : "F12",
"LA21_N" : "A10",
"LA21_P" : "B10",
"LA22_N" : "H12",
"LA22_P" : "H13",
"LA23_N" : "A11",
"LA23_P" : "B11",
"LA24_N" : "A6",
"LA24_P" : "B6",
"LA25_N" : "C6",
"LA25_P" : "C7",
"LA26_N" : "B8",
"LA26_P" : "B9",
"LA27_N" : "A7",
"LA27_P" : "A8",
"LA28_N" : "L13",
"LA28_P" : "M13",
"LA29_N" : "J10",
"LA29_P" : "K10",
"LA30_N" : "D9",
"LA30_P" : "E9",
"LA31_N" : "E7",
"LA31_P" : "F7",
"LA32_N" : "E8",
"LA32_P" : "F8",
"LA33_N" : "C8",
"LA33_P" : "C9",
}),
("FMC_HPC1", {
"CLK0_M2C_N" : "E23",
"CLK0_M2C_P" : "F23",
"DP0_C2M_N" : "AJ5",
"DP0_C2M_P" : "AJ6",
"DP0_M2C_N" : "AK3",
"DP0_M2C_P" : "AK4",
"LA00_CC_N" : "B19",
"LA00_CC_P" : "B18",
"LA01_CC_N" : "D24",
"LA01_CC_P" : "E24",
"LA02_N" : "K23",
"LA02_P" : "K22",
"LA03_N" : "J22",
"LA03_P" : "J21",
"LA04_N" : "H24",
"LA04_P" : "J24",
"LA05_N" : "G26",
"LA05_P" : "G25",
"LA06_N" : "H22",
"LA06_P" : "H21",
"LA07_N" : "C23",
"LA07_P" : "D22",
"LA08_N" : "H26",
"LA08_P" : "J25",
"LA09_N" : "F20",
"LA09_P" : "G20",
"LA10_N" : "E22",
"LA10_P" : "F22",
"LA11_N" : "A21",
"LA11_P" : "A20",
"LA12_N" : "D19",
"LA12_P" : "E19",
"LA13_N" : "C22",
"LA13_P" : "C21",
"LA14_N" : "D21",
"LA14_P" : "D20",
"LA15_N" : "A19",
"LA15_P" : "A18",
"LA16_N" : "C19",
"LA16_P" : "C18",
"GBTCLK0_M2C_C_N" : "Y7",
"GBTCLK0_M2C_C_P" : "Y8",
}),
]
# Platform -----------------------------------------------------------------------------------------
@ -125,7 +283,7 @@ class Platform(XilinxUSPPlatform):
default_clk_period = 1e9/125e6
def __init__(self, toolchain="vivado"):
XilinxUSPPlatform.__init__(self, "xczu7ev-ffvc1156-2-e", _io, toolchain=toolchain)
XilinxUSPPlatform.__init__(self, "xczu7ev-ffvc1156-2-e", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return VivadoProgrammer()