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mnt_rkx7: Switch DDR3 to IS43TR16512B now added to LiteDRAM.

This commit is contained in:
Florent Kermarrec 2021-09-30 15:45:40 +02:00
parent 9bcae49629
commit 1217e94218
1 changed files with 2 additions and 2 deletions
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4
litex_boards/targets/mnt_rkx7.py
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@ -18,7 +18,7 @@ from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.cores.bitbang import I2CMaster from litex.soc.cores.bitbang import I2CMaster
from litedram.modules import MT41K512M16 # FIXME: IS43TR16512B from litedram.modules import IS43TR16512B
from litedram.phy import s7ddrphy from litedram.phy import s7ddrphy
from liteeth.phy.s7rgmii import LiteEthPHYRGMII from liteeth.phy.s7rgmii import LiteEthPHYRGMII
@ -68,7 +68,7 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41K512M16(sys_clk_freq, "1:4"), module = IS43TR16512B(sys_clk_freq, "1:4"),
size = 0x40000000, size = 0x40000000,
l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_size = kwargs.get("l2_size", 8192),
) )