Merge pull request #379 from chmousset/add_t8_devkit
[enh] added efinix t8f81 dev kit
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Andrew Dennison <andrew@motec.com.au>
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# Copyright (c) 2022 Charles-Henri Mousset <ch.mousset@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from litex.build.generic_platform import *
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from litex.build.efinix.platform import EfinixPlatform
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from litex.build.efinix.programmer import EfinixAtmelProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk33", 0, Pins("C3"), IOStandard("3.3_V_LVTTL_/_LVCMOS")), # net PLL_IN
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# Buttons
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("user_btn", 0, Pins("G1"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
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("user_btn", 1, Pins("F1"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
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# Leds
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("user_led", 0, Pins("G4"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
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("user_led", 1, Pins("J2"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
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("user_led", 2, Pins("C2"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
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("user_led", 3, Pins("E3"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
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("user_led", 4, Pins("B3"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
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# SPIFlash (W25Q80DV)
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("spiflash", 0,
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Subsignal("cs_n", Pins("J4")), # net SPI_SS
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Subsignal("clk", Pins("H4")), # net SPI_SCLK
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Subsignal("mosi", Pins("F4")), # net SPI_MOSI
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Subsignal("miso", Pins("H3")), # net SPI_MISO
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#Subsignal("wp", Pins("")),
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#Subsignal("hold", Pins("")),
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IOStandard("3.3_V_LVTTL_/_LVCMOS")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# use "j3:1" reference for pin 1 of J3. This makes it a 1:1 translation with connector numbering
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("j3", "ZERO #N/A #N/A G5 F1 G4 E1 J3 C2 G3 D2 J2 E3 H2 D3 F3 C3 G1 B3 #N/A #N/A A2 A2"),
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("j4", "ZERO #N/A #N/A A5 B8 B5 C8 C5 D6 A6 B9 B6 C9 C6 D7 C7 D8 A8 D9 A9 E8 A2 A2"),
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("j5", "ZERO #N/A #N/A F8 J9 E7 J8 F7 G8 E6 H8 F6 J7 F5 G6 G9 H6 H9 J6 #N/A #N/A A2 A2"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(EfinixPlatform):
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default_clk_name = "clk33"
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default_clk_period = 1e9/33.333e6
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def __init__(self, toolchain="efinity"):
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EfinixPlatform.__init__(self, "T8F81C2", _io, _connectors, toolchain=toolchain)
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def create_programmer(self):
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return EfinixAtmelProgrammer()
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def do_finalize(self, fragment):
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EfinixPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk33", loose=True), 1e9/33.333e6)
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Andrew Dennison <andrew@motec.com.au>
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# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2022 Charles-Henri Mousset <ch.mousset@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import efinix_t8f81_dev_kit
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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clk33 = platform.request("clk33")
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rst_n = platform.request("user_btn", 0)
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# PLL.
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self.submodules.pll = pll = TRIONPLL(platform)
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self.comb += pll.reset.eq(~rst_n)
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pll.register_clkin(clk33, 33.333e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, bios_flash_offset, sys_clk_freq, with_led_chaser=True, **kwargs):
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platform = efinix_t8f81_dev_kit.Platform()
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# Disable Integrated ROM.
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kwargs["integrated_rom_size"] = 0
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# Set CPU variant / reset address
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if kwargs.get("cpu_type", "vexriscv") == "vexriscv":
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kwargs["cpu_variant"] = "minimal"
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Efinix T8F81 Dev Kit",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SPI Flash --------------------------------------------------------------------------------
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from litespi.modules import W25Q80BV
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=W25Q80BV(Codes.READ_1_1_1), with_master=False)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
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size = 32*kB,
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linker = True)
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)
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self.cpu.set_reset_address(self.bus.regions["rom"].origin)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Efinix T8F81C Dev Kit")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build bitstream.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
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target_group.add_argument("--sys-clk-freq", default=33.333e6, help="System clock frequency.")
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target_group.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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bios_flash_offset = int(args.bios_flash_offset, 0),
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.add_hex(0, builder.get_bitstream_filename(mode="sram"))
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prog.load()
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.add_hex(0, builder.get_bitstream_filename(mode="sram"))
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prog.add_bin(int(args.bios_flash_offset, 0), builder.get_bios_filename())
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prog.flash()
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if __name__ == "__main__":
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main()
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