sipeed_tang_primer_20k: Add initial DDR3 integration (WIP).

litex_boards/platforms/sipeed_tang_primer_20k.py

@@ -49,6 +49,34 @@ _io = [
         Subsignal("cd",   Pins("D15")),
         IOStandard("LVCMOS33"),
     ),
+
+    # DDR3 SDRAM IMD128M16R39CG8GNF-125
+    # DQ group L cannot work now
+    ("ddram", 0,
+        Subsignal("a", Pins("F7 A4 D6 F8 C4 E6 B1 D8 A5 F9 K3 B7 A3 C8"),
+            IOStandard("SSTL15")),
+        Subsignal("ba", Pins("H4 D3 H5"), IOStandard("SSTL15")),
+        Subsignal("ras_n", Pins("R4"), IOStandard("SSTL15")),
+        Subsignal("cas_n", Pins("R6"), IOStandard("SSTL15")),
+        Subsignal("we_n",  Pins("L2"), IOStandard("SSTL15")),
+        Subsignal("cs_n",  Pins("P5"), IOStandard("SSTL15")),
+        Subsignal("dm", Pins("K5"), IOStandard("SSTL15")),
+        #Subsignal("dm", Pins("G1 K5"), IOStandard("SSTL15")),
+        Subsignal("dq", Pins(
+            #"G5 F5 F4 F3 E2 C1 E1 B3",
+            "M3 K4 N2 L1 P4 H3 R1 M2"),
+            IOStandard("SSTL15"),
+            Misc("VREF=INTERNAL")),
+        #Subsignal("dqs_p", Pins("G2 J5"), IOStandard("SSTL15D")),
+        Subsignal("dqs_p", Pins("J5"), IOStandard("SSTL15D")),
+        #Subsignal("dqs_n", Pins("G3 K6"), IOStandard("SSTL15D")),
+        Subsignal("dqs_n", Pins("K6"), IOStandard("SSTL15D")),
+        Subsignal("clk_p", Pins("J1"), IOStandard("SSTL15D")),
+        Subsignal("clk_n", Pins("J3"), IOStandard("SSTL15D")),
+        Subsignal("cke",   Pins("J2"), IOStandard("SSTL15")),
+        Subsignal("odt",   Pins("R3"), IOStandard("SSTL15")),
+        Subsignal("reset_n", Pins("B9"), IOStandard("SSTL15")),
+    ),
 ]
 
 # Dock 204 Pins SODIMM Connector -------------------------------------------------------------------

litex_boards/targets/sipeed_tang_primer_20k.py

@@ -22,10 +22,9 @@ from liteeth.phy.rmii import LiteEthPHYRMII
 
 from litex_boards.platforms import sipeed_tang_primer_20k
 
-from litex.soc.cores.hyperbus import HyperRAM
-
-kB = 1024
-mB = 1024*kB
+from liteeth.phy.rmii import LiteEthPHYRMII
+from litedram.modules import MT41J128M16
+from litedram.phy import GW2DDRPHY
 
 # CRG ----------------------------------------------------------------------------------------------
 
@@ -34,16 +33,35 @@ class _CRG(Module):
         self.rst = Signal()
         self.clock_domains.cd_sys     = ClockDomain()
         self.clock_domains.cd_por     = ClockDomain()
+        self.clock_domains.cd_init    = ClockDomain()
+        self.clock_domains.cd_sys2x   = ClockDomain()
+        self.clock_domains.cd_sys2x_i = ClockDomain()
 
         # # #
 
+        self.stop  = Signal()
+        self.reset = Signal()
+
         # Clk
         clk27 = platform.request("clk27")
 
         # PLL
         self.submodules.pll = pll = GW2APLL(devicename=platform.devicename, device=platform.device)
         pll.register_clkin(clk27, 27e6)
-        pll.create_clkout(self.cd_sys, sys_clk_freq)
+        pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
+        self.specials += [
+            Instance("DHCEN",
+                i_CLKIN  = self.cd_sys2x_i.clk,
+                i_CE     = self.stop,
+                o_CLKOUT = self.cd_sys2x.clk),
+            Instance("CLKDIV",
+                p_DIV_MODE = "2",
+                i_CALIB    = 0,
+                i_HCLKIN   = self.cd_sys2x.clk,
+                i_RESETN   = ~self.reset,
+                o_CLKOUT   = self.cd_sys.clk),
+            AsyncResetSynchronizer(self.cd_sys, pll.reset | self.reset),
+        ]
 
         # Power on reset (the onboard POR is not aware of reprogramming)
         por_count = Signal(16, reset=2**16-1)
@@ -53,6 +71,10 @@ class _CRG(Module):
         self.sync.por += If(~por_done, por_count.eq(por_count - 1))
         self.comb += pll.reset.eq(~por_done)
 
+        # Init clock domain
+        self.comb += self.cd_init.clk.eq(clk27)
+        self.comb += self.cd_init.rst.eq(pll.reset)
+
         # Video PLL
         if with_video_pll:
             self.submodules.video_pll = video_pll = GW2APLL(devicename=platform.devicename, device=platform.device)
@@ -97,6 +119,20 @@ class BaseSoC(SoCCore):
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Primer 20K", **kwargs)
 
+        # DDR3 SDRAM -------------------------------------------------------------------------------
+        if not self.integrated_main_ram_size:
+            self.submodules.ddrphy = GW2DDRPHY(
+                platform.request("ddram"),
+                sys_clk_freq=sys_clk_freq)
+            self.ddrphy.settings.rtt_nom = "disabled"
+            self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
+            self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
+            self.add_sdram("sdram",
+                phy           = self.ddrphy,
+                module        = MT41J128M16(sys_clk_freq, "1:2"),
+                l2_cache_size = kwargs.get("l2_size", 0)
+            )
+
         # SPI Flash --------------------------------------------------------------------------------
         if with_spi_flash:
             from litespi.modules import W25Q32JV as SpiFlashModule