add qmtech_xc7l325t
This commit is contained in:
Hans Baier
parent
d33cf1a74c
commit
187080228c
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#
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# This file is part of LiteX-Boards.
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#
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk50", 0, Pins("F22"), IOStandard("LVCMOS33")),
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# SPIFlash
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# S25FL256L
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#("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
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# Subsignal("cs_n", Pins("C23")),
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# Subsignal("clk", Pins("C8")),
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# Subsignal("dq", Pins("B24", "A25", "B22", "A22")),
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# IOStandard("LVCMOS33")
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#),
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# DDR3 SDRAM
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# MT41J128M16JT-125K
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("ddram", 0,
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Subsignal("a", Pins("AF5 AF2 AD6 AC6 AD4 AB6 AE2 Y5 AA4 AE6 AE3 AD5 AB4 Y6"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AD3 AE1 AE5"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("AC3"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AC4"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AF4"), IOStandard("SSTL15")),
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#Subsignal("cs_n", Pins("--"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("V1 V3"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"W1 V2 Y1 Y3 AC2 Y2 AB2 AA3",
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"U1 V4 U6 W3 V6 U2 U7 U5"),
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IOStandard("SSTL15")), # _T_DCI")),
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Subsignal("dqs_p", Pins("AB1 W6"), IOStandard("DIFF_SSTL15")), # _T_DCI")),
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Subsignal("dqs_n", Pins("AC1 W5"), IOStandard("DIFF_SSTL15")), # _T_DCI")),
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Subsignal("clk_p", Pins("AA5"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("AB5"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("AD1"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("AF3"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("W4"), IOStandard("LVCMOS15")),
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Misc("SLEW=FAST"),
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),
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]
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# The connectors are named after the daughterboard, not the core board
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# because on the different core boards the names vary, but on the
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# daughterboard they stay the same, which we need to connect the
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# daughterboard peripherals to the core board.
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# On this board J2 is U5 and J3 is U4
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_connectors = [
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("J2", {
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# odd row even row
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7: "A8", 8: "A9",
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9: "B9", 10: "C9",
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11: "A10", 12: "B10",
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13: "D10", 14: "E10",
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15: "B11", 16: "B12",
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17: "C11", 18: "C12",
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19: "A12", 20: "A13",
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21: "D13", 22: "D14",
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23: "A14", 24: "B14",
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25: "C13", 26: "C14",
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27: "A15", 28: "B15",
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29: "D16", 30: "D15",
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31: "B16", 32: "C16",
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33: "A17", 34: "B17",
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35: "D18", 36: "E18",
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37: "C18", 38: "C17",
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39: "A19", 40: "A18",
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41: "B19", 42: "C19",
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43: "A20", 44: "B20",
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45: "D20", 46: "D19",
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47: "A24", 48: "A23",
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49: "E22", 50: "E21",
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51: "D24", 52: "D23",
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53: "D25", 54: "E25",
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55: "E26", 56: "F25",
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57: "B26", 58: "B25",
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59: "C26", 60: "D26",
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}),
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("J3", {
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# odd row even row
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7: "AD21", 8: "AE21",
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9: "AE22", 10: "AF22",
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11: "AE23", 12: "AF23",
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13: "V21", 14: "W21",
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15: "Y22", 16: "AA22",
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17: "AF24", 18: "AF25",
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19: "AB21", 20: "AC21",
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21: "AB22", 22: "AC22",
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23: "AD23", 24: "AD24",
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25: "AC23", 26: "AC24",
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27: "AD25", 28: "AE25",
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29: "AA23", 30: "AB24",
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31: "AA25", 32: "AB25",
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33: "Y23", 34: "AA24",
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35: "AD26", 36: "AE26",
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37: "AB26", 38: "AC26",
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39: "W23", 40: "W24",
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41: "Y25", 42: "Y26",
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43: "W25", 44: "W26",
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45: "U26", 46: "V26",
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47: "V23", 48: "V24",
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49: "U24", 50: "U25",
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51: "T22", 52: "T23",
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53: "R22", 54: "R23",
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55: "R25", 56: "P25",
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57: "P23", 58: "N23",
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59: "N26", 60: "M26",
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})
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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core_resources = [
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("onboard_led_1", 0, Pins("J26"), IOStandard("LVCMOS33")),
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("onboard_led_2", 0, Pins("H26"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("AD21"), IOStandard("LVCMOS33")),
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]
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def __init__(self, toolchain="yosys+nexpnr", with_daughterboard=False):
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device = "xc7k325tffg676-1"
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io = _io
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connectors = _connectors
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io += self.core_resources
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if with_daughterboard:
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from litex_boards.platforms.qmtech_daughterboard import QMTechDaughterboard
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daughterboard = QMTechDaughterboard(IOStandard("LVCMOS33"))
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io += daughterboard.io
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connectors += daughterboard.connectors
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XilinxPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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self.add_platform_command("set_property INTERNAL_VREF 0.90 [get_iobanks 33]")
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def create_programmer(self):
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bscan_spi = "bscan_spi_xc7k325t.bit"
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return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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@ -0,0 +1,281 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import qmtech_xc7k325t
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoVGAPHY
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41J128M16
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from litedram.phy import s7ddrphy
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from liteeth.phy.mii import LiteEthPHYMII
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# SevenSeg -----------------------------------------------------------------------------------------
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from migen.genlib.misc import WaitTimer
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from litex.soc.interconnect.csr import *
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class SevenSeg(Module, AutoCSR):
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def __init__(self, segs, sels, sys_clk_freq, period=1e-2):
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self.segs = segs
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self.sels = sels
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n = len(sels)
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self._out = CSRStorage(4*n, description="7 Seg LEDs Control.")
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xdigits = Signal(4*n)
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select = Signal(n)
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count = Signal(max=n)
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table = [
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0x3f, 0x06, 0x5b, 0x4f,
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0x66, 0x6d, 0x7d, 0x07,
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0x7f, 0x6f, 0x77, 0x7c,
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0x39, 0x5e, 0x79, 0x71
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]
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abcdefg = Signal(8)
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hexa = Signal(4)
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cases = {}
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for i in range(16):
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cases[i] = abcdefg.eq(table[i])
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self.comb += Case(hexa, cases)
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timer = WaitTimer(int(period*sys_clk_freq/(2*n)))
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self.submodules += timer
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self.comb += timer.wait.eq(~timer.done)
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self.sync += If(timer.done,
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If(count == n-1,
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count.eq(0),
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select.eq(1 << (n-1)),
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xdigits.eq(self._out.storage)
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).Else(
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count.eq(count + 1),
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select.eq(select >> 1),
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xdigits.eq(xdigits >> 4)
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)
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)
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self.comb += [
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hexa.eq(xdigits[0:4]),
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segs.eq(~abcdefg),
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sels.eq(select)
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]
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_ethernet, with_vga):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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if with_ethernet:
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self.clock_domains.cd_eth = ClockDomain()
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if with_vga:
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self.clock_domains.cd_vga = ClockDomain(reset_less=True)
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# # #
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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reset_button = platform.request("cpu_reset")
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self.comb += pll.reset.eq(~reset_button | self.rst)
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pll.register_clkin(platform.request("clk50"), 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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if with_ethernet:
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pll.create_clkout(self.cd_eth, 25e6)
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if with_vga:
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pll.create_clkout(self.cd_vga, 40e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, toolchain="yosys+nextpnr", sys_clk_freq=int(100e6), with_daughterboard=False,
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with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
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local_ip="", remote_ip="",
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with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, with_video_colorbars=False,
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with_jtagbone=True, with_spi_flash=False, **kwargs):
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platform = qmtech_xc7k325t.Platform(toolchain=toolchain, with_daughterboard=with_daughterboard)
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# SoCCore ----------------------------------------------------------------------------------
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print(f"{str(kwargs)}")
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if (kwargs["uart_name"] == "serial") and (not with_daughterboard):
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kwargs["uart_name"] = "gpio_serial"
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on QMTech XC7K325T" + (" + Daughterboard" if with_daughterboard else ""),
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet or with_etherbone, with_video_terminal or with_video_framebuffer or with_video_colorbars)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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from litedram.common import PHYPadsReducer
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
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pads = PHYPadsReducer(platform.request("ddram", 0), [0, 1]),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J128M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# The daughterboard has the tx clock wired to a non-clock pin, so we can't help it
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#self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]")
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self.add_constant("TARGET_BIOS_INIT", 1)
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if local_ip:
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local_ip = local_ip.split(".")
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self.add_constant("LOCALIP1", int(local_ip[0]))
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self.add_constant("LOCALIP2", int(local_ip[1]))
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self.add_constant("LOCALIP3", int(local_ip[2]))
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self.add_constant("LOCALIP4", int(local_ip[3]))
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if remote_ip:
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remote_ip = remote_ip.split(".")
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self.add_constant("REMOTEIP1", int(remote_ip[0]))
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self.add_constant("REMOTEIP2", int(remote_ip[1]))
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self.add_constant("REMOTEIP3", int(remote_ip[2]))
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self.add_constant("REMOTEIP4", int(remote_ip[3]))
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# Jtagbone ---------------------------------------------------------------------------------
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if with_jtagbone:
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self.add_jtagbone()
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import MT25QL128
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", module=MT25QL128(Codes.READ_1_1_1), with_master=True)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer or with_video_colorbars:
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self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga", format="rgb565")
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if with_video_colorbars:
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self.add_video_colorbars(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.submodules.sevenseg = SevenSeg(
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segs = platform.request_all("seven_seg"),
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sels = platform.request_all("seven_seg_ctl"),
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sys_clk_freq = sys_clk_freq)
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if not with_daughterboard and kwargs["uart_name"] == "serial":
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kwargs["uart_name"] = "jtag_serial"
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on QMTech XC7K325T")
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parser.add_argument("--toolchain", default="yosys+nextpnr", help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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parser.add_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.")
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ethopts = parser.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
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parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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parser.add_argument("--remote-ip", default="192.168.1.100",
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help="Remote IP address of TFTP server.")
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parser.add_argument("--local-ip", default="192.168.1.50",
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help="Local IP address.")
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sdopts = parser.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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parser.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
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parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
|
||||
viopts = parser.add_mutually_exclusive_group()
|
||||
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
|
||||
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).")
|
||||
viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (VGA).")
|
||||
builder_args(parser)
|
||||
soc_core_args(parser)
|
||||
vivado_build_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = BaseSoC(
|
||||
toolchain = args.toolchain,
|
||||
sys_clk_freq = int(float(args.sys_clk_freq)),
|
||||
with_daughterboard = args.with_daughterboard,
|
||||
with_ethernet = args.with_ethernet,
|
||||
with_etherbone = args.with_etherbone,
|
||||
eth_ip = args.eth_ip,
|
||||
eth_dynamic_ip = args.eth_dynamic_ip,
|
||||
local_ip = args.local_ip,
|
||||
remote_ip = args.remote_ip,
|
||||
with_jtagbone = args.with_jtagbone,
|
||||
with_spi_flash = args.with_spi_flash,
|
||||
with_video_terminal = args.with_video_terminal,
|
||||
with_video_framebuffer = args.with_video_framebuffer,
|
||||
with_video_colorbars = args.with_video_colorbars,
|
||||
**soc_core_argdict(args)
|
||||
)
|
||||
|
||||
if args.with_spi_sdcard:
|
||||
soc.add_spi_sdcard()
|
||||
if args.with_sdcard:
|
||||
soc.add_sdcard()
|
||||
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
if args.with_ethernet or args.with_etherbone:
|
||||
os.makedirs(os.path.join(builder.software_dir, "include/generated"),
|
||||
exist_ok=True)
|
||||
write_to_file(
|
||||
os.path.join(builder.software_dir, "include/generated", "target.h"),
|
||||
"// Force 100Base-T speed\n"
|
||||
"#define TARGET_ETHPHY_INIT_FUNC() mdio_write(0, 0, 0x2100)")
|
||||
|
||||
builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
|
||||
builder.build(**builder_kwargs, run=args.build)
|
||||
|
||||
if args.load:
|
||||
prog = soc.platform.create_programmer()
|
||||
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue