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Add with_led_chaser argument to constructor of boards using LedChaser submodule.

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This commit is contained in:
Joey Bushagour 2021-07-06 16:39:37 -05:00
parent 8c1e6c6a02
commit 1920db3535
64 changed files with 368 additions and 261 deletions
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4
litex_boards/targets/1bitsquared_icebreaker.py
View file

@ -70,7 +70,8 @@ class _CRG(Module):
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), with_video_terminal=False, **kwargs):
def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), with_led_chaser=True,
with_video_terminal=False, **kwargs):
platform = icebreaker.Platform()
platform.add_extension(icebreaker.break_off_pmod)
@ -111,6 +112,7 @@ class BaseSoC(SoCCore):
self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="sys")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/antmicro_lpddr4_test_board.py
View file

@ -55,7 +55,7 @@ class BaseSoC(SoCCore):
def __init__(self, *, sys_clk_freq=int(50e6), iodelay_clk_freq=200e6,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False,
ident_version=True, **kwargs):
with_led_chaser=True, ident_version=True, **kwargs):
platform = lpddr4_test_board.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -113,6 +113,7 @@ class BaseSoC(SoCCore):
self.add_uartbone("serial", baudrate=1e6)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

5
litex_boards/targets/camlink_4k.py
View file

@ -72,7 +72,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, toolchain="trellis", **kwargs):
def __init__(self, toolchain="trellis", with_led_chaser=True, **kwargs):
platform = camlink_4k.Platform(toolchain=toolchain)
sys_clk_freq = int(81e6)
@ -98,7 +98,8 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if platform.lookup_request("serial", loose=True) is None: # Disable leds when serial is used.
# Disable leds when serial is used.
if platform.lookup_request("serial", loose=True) is None and with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

7
litex_boards/targets/colorlight_5a_75x.py
View file

@ -119,7 +119,9 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, board, revision, sys_clk_freq=60e6, with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_phy=0, use_internal_osc=False, sdram_rate="1:1", **kwargs):
def __init__(self, board, revision, sys_clk_freq=60e6, with_ethernet=False,
with_etherbone=False, eth_ip="192.168.1.50", eth_phy=0, with_led_chaser=True,
use_internal_osc=False, sdram_rate="1:1", **kwargs):
board = board.lower()
assert board in ["5a-75b", "5a-75e"]
if board == "5a-75b":
@ -167,7 +169,8 @@ class BaseSoC(SoCCore):
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Leds -------------------------------------------------------------------------------------
if platform.lookup_request("serial", loose=True) is None: # Disable leds when serial is used.
# Disable leds when serial is used.
if platform.lookup_request("serial", loose=True) is None and with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led_n"),
sys_clk_freq = sys_clk_freq)

6
litex_boards/targets/colorlight_i5.py
View file

@ -99,7 +99,10 @@ class _CRG(Module):
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0xd0000000}}
def __init__(self, board="i5", revision="7.0", sys_clk_freq=60e6, with_ethernet=False, with_etherbone=False, local_ip="", remote_ip="", eth_phy=0, use_internal_osc=False, sdram_rate="1:1", with_video_terminal=False, with_video_framebuffer=False, **kwargs):
def __init__(self, board="i5", revision="7.0", sys_clk_freq=60e6, with_ethernet=False,
with_etherbone=False, local_ip="", remote_ip="", eth_phy=0, with_led_chaser=True,
use_internal_osc=False, sdram_rate="1:1", with_video_terminal=False,
with_video_framebuffer=False, **kwargs):
board = board.lower()
assert board in ["i5"]
if board == "i5":
@ -117,6 +120,7 @@ class BaseSoC(SoCCore):
self.submodules.crg = _CRG(platform, sys_clk_freq, use_internal_osc=use_internal_osc, with_usb_pll=with_usb_pll, with_video_pll=with_video_pll, sdram_rate=sdram_rate)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
ledn = platform.request_all("user_led_n")
self.submodules.leds = LedChaser(pads=ledn, sys_clk_freq=sys_clk_freq)

6
litex_boards/targets/digilent_arty.py
View file

@ -61,7 +61,10 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, ident_version=True, with_jtagbone=True, with_mapped_flash=False, **kwargs):
def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=int(100e6),
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50",
eth_dynamic_ip=False, ident_version=True, with_led_chaser=True, with_jtagbone=True,
with_mapped_flash=False, **kwargs):
platform = arty.Platform(variant=variant, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
@ -107,6 +110,7 @@ class BaseSoC(SoCCore):
self.bus.add_slave(name="spiflash", slave=self.spiflash_mmap.bus, region=spiflash_region)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/digilent_arty_s7.py
View file

@ -51,7 +51,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, variant="s7-50", sys_clk_freq=int(100e6), **kwargs):
def __init__(self, variant="s7-50", sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
platform = arty_s7.Platform(variant=variant)
# SoCCore ----------------------------------------------------------------------------------
@ -76,6 +76,7 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/digilent_basys3.py
View file

@ -40,7 +40,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6), with_video_terminal=False, **kwargs):
def __init__(self, sys_clk_freq=int(75e6), with_led_chaser=True, with_video_terminal=False, **kwargs):
platform = basys3.Platform()
# SoCCore ----------------------------------_-----------------------------------------------
@ -59,6 +59,7 @@ class BaseSoC(SoCCore):
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/digilent_genesys2.py
View file

@ -47,7 +47,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, **kwargs):
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False,
with_led_chaser=True, **kwargs):
platform = genesys2.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -82,6 +83,7 @@ class BaseSoC(SoCCore):
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

5
litex_boards/targets/digilent_nexys4ddr.py
View file

@ -54,7 +54,9 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False, with_video_terminal=False, with_video_framebuffer=False, **kwargs):
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False,
with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
**kwargs):
platform = nexys4ddr.Platform()
# SoCCore ----------------------------------_-----------------------------------------------
@ -97,6 +99,7 @@ class BaseSoC(SoCCore):
self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

5
litex_boards/targets/digilent_nexys_video.py
View file

@ -71,7 +71,9 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_sata=False, vadj="1.2V", with_video_terminal=False, with_video_framebuffer=False, **kwargs):
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False,
with_led_chaser=True, with_sata=False, vadj="1.2V", with_video_terminal=False,
with_video_framebuffer=False, **kwargs):
platform = nexys_video.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
@ -141,6 +143,7 @@ class BaseSoC(SoCCore):
self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/ego1.py
View file

@ -39,7 +39,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), with_vga=False, **kwargs):
def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_vga=False, **kwargs):
platform = ego1.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -65,6 +65,7 @@ class BaseSoC(SoCCore):
]
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/enclustra_mercury_kx2.py
View file

@ -46,7 +46,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs):
platform = mercury_kx2.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -71,6 +71,7 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/enclustra_mercury_xu5.py
View file

@ -54,7 +54,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs):
platform = mercury_xu5.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -79,6 +79,7 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/fpc_iii.py
View file

@ -80,7 +80,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(80e6), toolchain="trellis", with_ethernet=False, with_etherbone=False, **kwargs):
def __init__(self, sys_clk_freq=int(80e6), toolchain="trellis", with_ethernet=False,
with_etherbone=False, with_led_chaser=True, **kwargs):
platform = fpc_iii.Platform(toolchain=toolchain)
# Serial -----------------------------------------------------------------------------------
@ -123,6 +124,7 @@ class BaseSoC(SoCCore):
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/gsd_orangecrab.py
View file

@ -147,7 +147,7 @@ class _CRGSDRAM(Module):
class BaseSoC(SoCCore):
def __init__(self, revision="0.2", device="25F", sdram_device="MT41K64M16",
sys_clk_freq=int(48e6), toolchain="trellis", **kwargs):
sys_clk_freq=int(48e6), toolchain="trellis", with_led_chaser=True, **kwargs):
platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain)
# Serial -----------------------------------------------------------------------------------
@ -197,6 +197,7 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/kosagi_fomu.py
View file

@ -70,7 +70,7 @@ class _CRG(Module):
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), **kwargs):
def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), with_led_chaser=True, **kwargs):
kwargs["uart_name"] = "usb_acm" # Enforce UART to USB-ACM
platform = fomu_pvt.Platform()
@ -110,6 +110,7 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led_n"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/kosagi_netv2.py
View file

@ -61,7 +61,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, variant="a7-35", sys_clk_freq=int(100e6), with_pcie=False, with_ethernet=False, **kwargs):
def __init__(self, variant="a7-35", sys_clk_freq=int(100e6), with_pcie=False,
with_ethernet=False, with_led_chaser=True, **kwargs):
platform = netv2.Platform(variant=variant)
# SoCCore ----------------------------------------------------------------------------------
@ -100,6 +101,7 @@ class BaseSoC(SoCCore):
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/lambdaconcept_ecpix5.py
View file

@ -78,7 +78,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, device="85F", sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False, **kwargs):
def __init__(self, device="85F", sys_clk_freq=int(75e6), with_ethernet=False,
with_etherbone=False, with_led_chaser=True, **kwargs):
platform = ecpix5.Platform(device=device, toolchain="trellis")
# SoCCore ----------------------------------------------------------------------------------
@ -115,6 +116,7 @@ class BaseSoC(SoCCore):
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
leds_pads = []
for i in range(4):
rgb_led_pads = platform.request("rgb_led", i)

3
litex_boards/targets/lattice_crosslink_nx_evn.py
View file

@ -68,7 +68,7 @@ class BaseSoC(SoCCore):
"sram" : 0x40000000,
"csr" : 0xf0000000,
}
def __init__(self, sys_clk_freq=int(75e6), toolchain="radiant", **kwargs):
def __init__(self, sys_clk_freq=int(75e6), toolchain="radiant", with_led_chaser=True, **kwargs):
platform = crosslink_nx_evn.Platform(toolchain=toolchain)
platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
@ -93,6 +93,7 @@ class BaseSoC(SoCCore):
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, size)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(14)]),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/lattice_crosslink_nx_vip.py
View file

@ -69,7 +69,8 @@ class BaseSoC(SoCCore):
"sram": 0x40000000,
"csr": 0xf0000000,
}
def __init__(self, sys_clk_freq=int(75e6), hyperram="none", toolchain="radiant", **kwargs):
def __init__(self, sys_clk_freq=int(75e6), hyperram="none", toolchain="radiant",
with_led_chaser=True, **kwargs):
platform = crosslink_nx_vip.Platform(toolchain=toolchain)
platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
@ -98,6 +99,7 @@ class BaseSoC(SoCCore):
self.register_mem("sram", self.mem_map["sram"], self.hyperram.bus, size)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(4)]),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/lattice_ecp5_evn.py
View file

@ -45,7 +45,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="trellis", **kwargs):
def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="trellis",
with_led_chaser=True, **kwargs):
platform = ecp5_evn.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
@ -59,6 +60,7 @@ class BaseSoC(SoCCore):
self.submodules.crg = crg
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/lattice_ice40up5k_evn.py
View file

@ -63,7 +63,7 @@ class _CRG(Module):
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), **kwargs):
def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), with_led_chaser=True, **kwargs):
platform = lattice_ice40up5k_evn.Platform()
# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
@ -98,6 +98,7 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led_n"),
sys_clk_freq = sys_clk_freq)

5
litex_boards/targets/lattice_versa_ecp5.py
View file

@ -78,7 +78,9 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6), device="LFE5UM5G", with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_phy=0, toolchain="trellis", **kwargs):
def __init__(self, sys_clk_freq=int(75e6), device="LFE5UM5G", with_ethernet=False,
with_etherbone=False, with_led_chaser=True, eth_ip="192.168.1.50", eth_phy=0,
toolchain="trellis", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain, device=device)
# FIXME: adapt integrated rom size for Microwatt
@ -120,6 +122,7 @@ class BaseSoC(SoCCore):
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/linsn_rv901t.py
View file

@ -50,7 +50,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs):
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, with_led_chaser=True, **kwargs):
platform = linsn_rv901t.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -79,6 +79,7 @@ class BaseSoC(SoCCore):
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

2
litex_boards/targets/logicbone.py
View file

@ -94,6 +94,7 @@ class BaseSoC(SoCCore):
def __init__(self, revision="rev0", device="45F", sdram_device="MT41K512M16",
sys_clk_freq = int(75e6),
with_ethernet = False,
with_led_chaser = True,
toolchain = "trellis",
**kwargs):
platform = logicbone.Platform(revision=revision, device=device ,toolchain=toolchain)
@ -142,6 +143,7 @@ class BaseSoC(SoCCore):
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/mist.py
View file

@ -54,7 +54,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), with_video_terminal=False, **kwargs):
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_video_terminal=False,
**kwargs):
platform = mist.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -81,6 +82,7 @@ class BaseSoC(SoCCore):
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/muselab_icesugar.py
View file

@ -58,7 +58,8 @@ class _CRG(Module):
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), with_video_terminal=False, **kwargs):
def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), with_led_chaser=True,
with_video_terminal=False, **kwargs):
platform = muselab_icesugar.Platform()
# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
@ -93,6 +94,7 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
led_pads = platform.request_all("user_led_n")
self.submodules.leds = LedChaser(
pads = led_pads,

3
litex_boards/targets/numato_aller.py
View file

@ -56,7 +56,7 @@ class CRG(Module):
# BaseSoC -----------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, **kwargs):
def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_pcie=False, **kwargs):
platform = aller.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -91,6 +91,7 @@ class BaseSoC(SoCCore):
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/numato_mimas_a7.py
View file

@ -51,7 +51,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_ethernet=False,
**kwargs):
platform = mimas_a7.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -83,6 +84,7 @@ class BaseSoC(SoCCore):
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/numato_tagus.py
View file

@ -57,7 +57,7 @@ class CRG(Module):
# BaseSoC -----------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, **kwargs):
def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_pcie=False, **kwargs):
platform = tagus.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -91,6 +91,7 @@ class BaseSoC(SoCCore):
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/pano_logic_g2.py
View file

@ -44,7 +44,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, revision, sys_clk_freq=int(50e6), with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", **kwargs):
def __init__(self, revision, sys_clk_freq=int(50e6), with_ethernet=False, with_etherbone=False,
eth_ip="192.168.1.50", with_led_chaser=True, **kwargs):
platform = pano_logic_g2.Platform(revision=revision)
if with_etherbone:
sys_clk_freq = int(125e6)
@ -71,6 +72,7 @@ class BaseSoC(SoCCore):
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/qmtech_ep4ce15.py
View file

@ -75,7 +75,7 @@ class _CRG(Module):
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), with_daughterboard=False,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_video_terminal=False, with_video_framebuffer=False,
with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
ident_version=True, sdram_rate="1:1", **kwargs):
platform = qmtech_ep4ce15.Platform(with_daughterboard=with_daughterboard)
@ -120,6 +120,7 @@ class BaseSoC(SoCCore):
self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

5
litex_boards/targets/qmtech_wukong.py
View file

@ -74,7 +74,9 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", with_video_terminal=False, with_video_framebuffer=False, video_timing="640x480@60Hz", **kwargs):
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False,
eth_ip="192.168.1.50", with_led_chaser=True, with_video_terminal=False,
with_video_framebuffer=False, video_timing="640x480@60Hz", **kwargs):
platform = qmtech_wukong.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -111,6 +113,7 @@ class BaseSoC(SoCCore):
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/qmtech_xc7a35t.py
View file

@ -76,7 +76,7 @@ class _CRG(Module):
class BaseSoC(SoCCore):
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_daughterboard=False,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_video_terminal=False, with_video_framebuffer=False,
with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
ident_version=True, with_jtagbone=True, with_mapped_flash=False, **kwargs):
platform = qmtech_xc7a35t.Platform(toolchain=toolchain, with_daughterboard=with_daughterboard)
@ -133,6 +133,7 @@ class BaseSoC(SoCCore):
self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/radiona_ulx3s.py
View file

@ -92,7 +92,8 @@ class _CRG(Module):
class BaseSoC(SoCCore):
def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis",
sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1",
with_video_terminal=False, with_video_framebuffer=False, spiflash=False, **kwargs):
with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
spiflash=False, **kwargs):
platform = ulx3s.Platform(device=device, revision=revision, toolchain=toolchain)
if spiflash:
self.mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
@ -130,6 +131,7 @@ class BaseSoC(SoCCore):
self.comb += platform.request("ext0p").eq(self.video_framebuffer.underflow) # FIXME: Remove, used to debug SDRAM underflows.
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/redpitaya.py
View file

@ -47,7 +47,7 @@ class _CRG(Module):
class BaseSoC(SoCCore):
def __init__(self, board, sys_clk_freq=int(100e6), **kwargs):
def __init__(self, board, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
platform = redpitaya.Platform(board)
if kwargs["uart_name"] == "serial":
@ -83,6 +83,7 @@ class BaseSoC(SoCCore):
self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/saanlima_pipistrello.py
View file

@ -153,7 +153,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, **kwargs):
def __init__(self, with_led_chaser=True, **kwargs):
sys_clk_freq = (83 + Fraction(1, 3))*1000*1000
platform = pipistrello.Platform()
@ -185,6 +185,7 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/scarabhardware_minispartan6.py
View file

@ -68,7 +68,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(80e6), sdram_rate="1:1", with_video_terminal=False, with_video_framebuffer=False, **kwargs):
def __init__(self, sys_clk_freq=int(80e6), sdram_rate="1:1", with_led_chaser=True,
with_video_terminal=False, with_video_framebuffer=False, **kwargs):
platform = minispartan6.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -100,6 +101,7 @@ class BaseSoC(SoCCore):
self.add_video_framebuffer(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/simple.py
View file

@ -23,7 +23,7 @@ from litex.soc.cores.led import LedChaser
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, platform, with_ethernet=False, **kwargs):
def __init__(self, platform, with_ethernet=False, with_led_chaser=True, **kwargs):
sys_clk_freq = int(1e9/platform.default_clk_period)
# SoCCore ----------------------------------------------------------------------------------
@ -37,6 +37,7 @@ class BaseSoC(SoCCore):
# Leds -------------------------------------------------------------------------------------
try:
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/sqrl_acorn.py
View file

@ -72,7 +72,8 @@ class CRG(Module):
# BaseSoC -----------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, variant="cle-215+", sys_clk_freq=int(100e6), with_pcie=False, with_sata=False, **kwargs):
def __init__(self, variant="cle-215+", sys_clk_freq=int(100e6), with_led_chaser=True,
with_pcie=False, with_sata=False, **kwargs):
platform = acorn.Platform(variant=variant)
# SoCCore ----------------------------------------------------------------------------------
@ -157,6 +158,7 @@ class BaseSoC(SoCCore):
self.add_sata(phy=self.sata_phy, mode="read+write")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/sqrl_fk33.py
View file

@ -43,7 +43,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs):
def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, with_pcie=False, **kwargs):
platform = fk33.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -92,6 +92,7 @@ class BaseSoC(SoCCore):
self.add_constant(k + "_INTERRUPT", i)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/sqrl_xcu1525.py
View file

@ -57,7 +57,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6), ddram_channel=0, with_pcie=False, with_sata=False, **kwargs):
def __init__(self, sys_clk_freq=int(125e6), ddram_channel=0, with_led_chaser=True,
with_pcie=False, with_sata=False, **kwargs):
platform = xcu1525.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -126,6 +127,7 @@ class BaseSoC(SoCCore):
self.add_sata(phy=self.sata_phy, mode="read+write")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/terasic_de0nano.py
View file

@ -59,7 +59,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), sdram_rate="1:1", **kwargs):
def __init__(self, sys_clk_freq=int(50e6), sdram_rate="1:1", with_led_chaser=True, **kwargs):
platform = de0nano.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -82,6 +82,7 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/terasic_de10lite.py
View file

@ -54,7 +54,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), with_video_terminal=False, **kwargs):
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_video_terminal=False,
**kwargs):
platform = de10lite.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -81,6 +82,7 @@ class BaseSoC(SoCCore):
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/terasic_de10nano.py
View file

@ -64,7 +64,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), with_mister_sdram=True, with_mister_video_terminal=False, sdram_rate="1:1", **kwargs):
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_mister_sdram=True,
with_mister_video_terminal=False, sdram_rate="1:1", **kwargs):
platform = de10nano.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -92,6 +93,7 @@ class BaseSoC(SoCCore):
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/terasic_deca.py
View file

@ -52,7 +52,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), with_video_terminal=False, **kwargs):
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_video_terminal=False,
**kwargs):
self.platform = platform = deca.Platform()
# Defaults to JTAG-UART since no hardware UART.
@ -74,6 +75,7 @@ class BaseSoC(SoCCore):
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/terasic_sockit.py
View file

@ -107,7 +107,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), revision="revd", sdram_rate="1:2", mister_sdram=None, with_video_terminal=False, **kwargs):
def __init__(self, sys_clk_freq=int(50e6), revision="revd", sdram_rate="1:2", mister_sdram=None,
with_led_chaser=True, with_video_terminal=False, **kwargs):
platform = terasic_sockit.Platform(revision)
# Defaults to UART over JTAG because serial is attached to the HPS and cannot be used.
@ -143,6 +144,7 @@ class BaseSoC(SoCCore):
self.add_video_terminal(phy=self.videophy, timings="1024x768@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/tinyfpga_bx.py
View file

@ -29,7 +29,7 @@ mB = 1024*kB
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
def __init__(self, bios_flash_offset, sys_clk_freq=int(16e6), **kwargs):
def __init__(self, bios_flash_offset, sys_clk_freq=int(16e6), with_led_chaser=True, **kwargs):
platform = tinyfpga_bx.Platform()
# Disable Integrated ROM since too large for iCE40.
@ -58,6 +58,7 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/trellisboard.py
View file

@ -111,7 +111,8 @@ class _CRGSDRAM(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", with_ethernet=False, **kwargs):
def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", with_ethernet=False,
with_led_chaser=True, **kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
@ -145,6 +146,7 @@ class BaseSoC(SoCCore):
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/trenz_c10lprefkit.py
View file

@ -58,7 +58,7 @@ class BaseSoC(SoCCore):
}
mem_map.update(SoCCore.mem_map)
def __init__(self, sys_clk_freq=int(50e6), with_ethernet=False, **kwargs):
def __init__(self, sys_clk_freq=int(50e6), with_ethernet=False, with_led_chaser=True, **kwargs):
platform = c10lprefkit.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -92,6 +92,7 @@ class BaseSoC(SoCCore):
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/trenz_cyc1000.py
View file

@ -47,7 +47,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, **kwargs):
platform = cyc1000.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -69,6 +69,7 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/trenz_max1000.py
View file

@ -47,7 +47,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, **kwargs):
platform = max1000.Platform()
kwargs["integrated_rom_size"] = 0x6000
@ -72,6 +72,7 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/trenz_te0725.py
View file

@ -44,7 +44,7 @@ class BaseSoC(SoCCore):
}
}
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
platform = trenz_te0725.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -63,6 +63,7 @@ class BaseSoC(SoCCore):
self.register_mem("hyperram", self.mem_map["hyperram"], self.hyperram.bus, size)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/trenz_tec0117.py
View file

@ -53,7 +53,8 @@ class _CRG(Module):
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
def __init__(self, bios_flash_offset, sys_clk_freq=int(25e6), sdram_rate="1:1", **kwargs):
def __init__(self, bios_flash_offset, sys_clk_freq=int(25e6), sdram_rate="1:1",
with_led_chaser=True, **kwargs):
platform = tec0117.Platform()
# Use custom default configuration to fit in LittleBee.
@ -113,6 +114,7 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/xilinx_ac701.py
View file

@ -56,7 +56,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, eth_phy="rgmii", with_pcie=False, **kwargs):
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, eth_phy="rgmii",
with_led_chaser=True, with_pcie=False, **kwargs):
platform = ac701.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -127,6 +128,7 @@ class BaseSoC(SoCCore):
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/xilinx_alveo_u250.py
View file

@ -58,7 +58,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs):
def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, with_pcie=False, **kwargs):
platform = alveo_u250.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -95,6 +95,7 @@ class BaseSoC(SoCCore):
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/xilinx_kc705.py
View file

@ -52,7 +52,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_pcie=False, with_sata=False, **kwargs):
def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_led_chaser=True,
with_pcie=False, with_sata=False, **kwargs):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -126,6 +127,7 @@ class BaseSoC(SoCCore):
self.add_sata(phy=self.sata_phy, mode="read+write")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

5
litex_boards/targets/xilinx_kcu105.py
View file

@ -61,7 +61,9 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", with_pcie=False, with_sata=False, **kwargs):
def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False,
eth_ip="192.168.1.50", with_led_chaser=True, with_pcie=False, with_sata=False,
**kwargs):
platform = kcu105.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -140,6 +142,7 @@ class BaseSoC(SoCCore):
self.add_sata(phy=self.sata_phy, mode="read+write")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/xilinx_vc707.py
View file

@ -48,7 +48,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs):
def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, with_pcie=False, **kwargs):
platform = vc707.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -80,6 +80,7 @@ class BaseSoC(SoCCore):
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/xilinx_vcu118.py
View file

@ -55,7 +55,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs):
platform = vcu118.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -81,6 +81,7 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/xilinx_zcu104.py
View file

@ -56,7 +56,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs):
platform = zcu104.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -82,6 +82,7 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

3
litex_boards/targets/xilinx_zybo_z7.py
View file

@ -45,7 +45,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
platform = zybo_z7.Platform()
if kwargs["uart_name"] == "serial": kwargs["uart_name"] = "usb_uart" # Use USB-UART Pmod on JB.
@ -76,6 +76,7 @@ class BaseSoC(SoCCore):
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)

4
litex_boards/targets/ztex213.py
View file

@ -62,7 +62,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, variant="ztex2.13a", sys_clk_freq=int(100e6), expansion="debug", **kwargs):
def __init__(self, variant="ztex2.13a", sys_clk_freq=int(100e6), expansion="debug",
with_led_chaser=True, **kwargs):
platform = ztex213.Platform(variant=variant, expansion=expansion)
# SoCCore ----------------------------------------------------------------------------------
@ -87,6 +88,7 @@ class BaseSoC(SoCCore):
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)