efinix_trion_t120_bga576: Add SPIFlash support (X1 for now).
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03c34e31cd
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@ -37,6 +37,23 @@ _io = [
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("user_sw", 2, Pins("T15"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
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("user_sw", 3, Pins("U15"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("R23")),
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Subsignal("clk", Pins("P22")),
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Subsignal("mosi", Pins("N24")),
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Subsignal("miso", Pins("N23")),
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#Subsignal("wp", Pins("R19")),
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#Subsignal("hold", Pins("R17")),
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IOStandard("3.3_V_LVTTL_/_LVCMOS")
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("R23")),
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Subsignal("clk", Pins("P22")),
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Subsignal("dq", Pins("N24 N23 R19 R17")),
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IOStandard("3.3_V_LVTTL_/_LVCMOS")
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),
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# RGMII Ethernet
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("eth_clocks", 0,
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@ -40,7 +40,7 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
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def __init__(self, sys_clk_freq=int(100e6), with_spi_flash=False, with_led_chaser=True, **kwargs):
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platform = efinix_trion_t120_bga576_dev_kit.Platform()
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# USBUART PMOD as Serial--------------------------------------------------------------------
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@ -60,6 +60,12 @@ class BaseSoC(SoCCore):
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import W25Q128JV
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=W25Q128JV(Codes.READ_1_1_1), with_master=True)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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@ -70,14 +76,18 @@ class BaseSoC(SoCCore):
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Efinix Trion T120 BGA576 Dev Kit")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
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parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(int(float(args.sys_clk_freq)), **soc_core_argdict(args))
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_spi_flash = args.with_spi_flash,
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**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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