targets/panol_logic_g2: replace with a minimal target.

litex_boards/targets/pano_logic_g2.py

@@ -1,224 +1,61 @@
-# This file is Copyright (c) 2019 Tom Keddie <git@bronwenandtom.com>
+#!/usr/bin/env python3
-# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
+
+# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
-# Support for the Pano Logic Zero Client G2
+import os
-from migen import *
+import argparse
-
-from litex.soc.integration.soc_sdram import *
-from litex.soc.integration.builder import *
-from litex.soc.interconnect import wishbone
-
-from litedram.modules import MT47H32M16
-from litedram.phy import s6ddrphy
-from litedram.core import ControllerSettings
-
-from gateware import cas
-from gateware import info
-from gateware import spi_flash
-
-# Support for the Pano Logic Zero Client G2
 
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from litex_boards.platforms import pano_logic_g2
+
+from litex.soc.cores.clock import *
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+
+# CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
-    def __init__(self, platform, sys_clk_freq):
+    def __init__(self, platform, clk_freq):
         self.clock_domains.cd_sys    = ClockDomain()
-        self.clock_domains.cd_sdram_half = ClockDomain()
-        self.clock_domains.cd_sdram_full_wr = ClockDomain()
-        self.clock_domains.cd_sdram_full_rd = ClockDomain()
 
-        self.reset = Signal()
+        # # #
 
-        f0 = int(125e6)
+        self.submodules.pll = pll = S6PLL(speedgrade=-2)
+        pll.register_clkin(platform.request("clk125"), 125e6)
+        pll.create_clkout(self.cd_sys, clk_freq)
 
-        clk125 = platform.request(platform.default_clk_name)
+# BaseSoC ------------------------------------------------------------------------------------------
-        clk125a = Signal()
 
-        self.specials += Instance("IBUFG", i_I=clk125, o_O=clk125a)
+class BaseSoC(SoCCore):
+    def __init__(self, sys_clk_freq=int(50e6), **kwargs):
+        platform = pano_logic_g2.Platform()
 
-        clk125b = Signal()
+        # SoCCore ----------------------------------------------------------------------------------
-
+        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-        self.specials += Instance(
-            "BUFIO2", p_DIVIDE=1,
-            p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
-            i_I=clk125a, o_DIVCLK=clk125b)
-
-        unbuf_sdram_full = Signal()
-        unbuf_sdram_half_a = Signal()
-        unbuf_sdram_half_b = Signal()
-        unbuf_encoder = Signal()
-        unbuf_sys = Signal()
-        unbuf_unused = Signal()
-
-        # PLL signals
-        pll_lckd = Signal()
-        pll_fb = Signal()
-        self.specials.pll = Instance(
-            "PLL_ADV",
-            name="crg_pll_adv",
-            p_SIM_DEVICE="SPARTAN6", p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
-            p_REF_JITTER=.01,
-            i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
-            p_DIVCLK_DIVIDE=1,
-            # Input Clocks (125MHz)
-            i_CLKIN1=clk125b,
-            p_CLKIN1_PERIOD=platform.default_clk_period,
-            i_CLKIN2=0,
-            p_CLKIN2_PERIOD=0.,
-            i_CLKINSEL=1,
-            # Feedback
-            # (1000MHz) vco
-            i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
-            p_CLK_FEEDBACK="CLKFBOUT",
-            p_CLKFBOUT_MULT=8, p_CLKFBOUT_PHASE=0.,
-            # (200MHz) sdram wr rd
-            o_CLKOUT0=unbuf_sdram_full, p_CLKOUT0_DUTY_CYCLE=.5,
-            p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=5,
-            # (100MHz) unused
-            o_CLKOUT1=unbuf_encoder, p_CLKOUT1_DUTY_CYCLE=.5,
-            p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=10,
-            # (100MHz) sdram_half - sdram dqs adr ctrl
-            o_CLKOUT2=unbuf_sdram_half_a, p_CLKOUT2_DUTY_CYCLE=.5,
-            p_CLKOUT2_PHASE=270., p_CLKOUT2_DIVIDE=10,
-            # (100MHz) off-chip ddr
-            o_CLKOUT3=unbuf_sdram_half_b, p_CLKOUT3_DUTY_CYCLE=.5,
-            p_CLKOUT3_PHASE=250., p_CLKOUT3_DIVIDE=10,
-            # (100MHz) unused
-            o_CLKOUT4=unbuf_unused, p_CLKOUT4_DUTY_CYCLE=.5,
-            p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=10,
-            # ( 50MHz) sysclk
-            o_CLKOUT5=unbuf_sys, p_CLKOUT5_DUTY_CYCLE=.5,
-            p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=20,
-        )
-
-        # power on reset?
-        reset = ~platform.request("cpu_reset") | self.reset
-        self.clock_domains.cd_por = ClockDomain()
-        por = Signal(max=1 << 11, reset=(1 << 11) - 1)
-        self.sync.por += If(por != 0, por.eq(por - 1))
-        self.specials += AsyncResetSynchronizer(self.cd_por, reset)
-
-        # System clock - 50MHz
-        self.specials += Instance("BUFG", name="sys_bufg", i_I=unbuf_sys, o_O=self.cd_sys.clk)
-        self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
-        self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | (por > 0))
-
-        # SDRAM clocks
-        # ------------------------------------------------------------------------------
-        self.clk4x_wr_strb = Signal()
-        self.clk4x_rd_strb = Signal()
-
-        # sdram_full
-        self.specials += Instance("BUFPLL", name="sdram_full_bufpll",
-                                  p_DIVIDE=4,
-                                  i_PLLIN=unbuf_sdram_full, i_GCLK=self.cd_sys.clk,
-                                  i_LOCKED=pll_lckd,
-                                  o_IOCLK=self.cd_sdram_full_wr.clk,
-                                  o_SERDESSTROBE=self.clk4x_wr_strb)
-        self.comb += [
-            self.cd_sdram_full_rd.clk.eq(self.cd_sdram_full_wr.clk),
-            self.clk4x_rd_strb.eq(self.clk4x_wr_strb),
-        ]
-        # sdram_half
-        self.specials += Instance("BUFG", name="sdram_half_a_bufpll", i_I=unbuf_sdram_half_a, o_O=self.cd_sdram_half.clk)
-        clk_sdram_half_shifted = Signal()
-        self.specials += Instance("BUFG", name="sdram_half_b_bufpll", i_I=unbuf_sdram_half_b, o_O=clk_sdram_half_shifted)
-
-        output_clk = Signal()
-        clk = platform.request("ddram_clock_b")
-        self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
-                                  p_INIT=0, p_SRTYPE="SYNC",
-                                  i_D0=1, i_D1=0, i_S=0, i_R=0, i_CE=1,
-                                  i_C0=clk_sdram_half_shifted,
-                                  i_C1=~clk_sdram_half_shifted,
-                                  o_Q=output_clk)
-        self.specials += Instance("OBUFDS", i_I=output_clk, o_O=clk.p, o_OB=clk.n)
-
-
-from targets.utils import dict_set_max
-
-class BaseSoC(SoCSDRAM):
-    mem_map = {**SoCSDRAM.mem_map, **{
-        'spiflash': 0x20000000,
-    }}
-
-    def __init__(self, platform, **kwargs):
-        dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
-        dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
-
-        sys_clk_freq = int(50e6)
-        # SoCSDRAM ---------------------------------------------------------------------------------
-        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
-        self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
 
-        # DDR2 SDRAM -------------------------------------------------------------------------------
+# Build --------------------------------------------------------------------------------------------
-        if True:
-            sdram_module = MT47H32M16(sys_clk_freq, "1:2")
-            self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
-                platform.request("ddram_b"),
-                memtype      = sdram_module.memtype,
-                rd_bitslip   = 0,
-                wr_bitslip   = 4,
-                dqs_ddr_alignment="C0")
-            self.add_csr("ddrphy")
-            controller_settings = ControllerSettings(
-                with_bandwidth=True)
-            self.register_sdram(
-                self.ddrphy,
-                geom_settings   = sdram_module.geom_settings,
-                timing_settings = sdram_module.timing_settings,
-                controller_settings=controller_settings)
-            self.comb += [
-                self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
-                self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
-            ]
 
-        # Basic peripherals ------------------------------------------------------------------------
+def main():
-        # info module
+    parser = argparse.ArgumentParser(description="LiteX SoC on Pano Logic G2")
-        self.submodules.info = info.Info(platform, self.__class__.__name__)
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
-        self.add_csr("info")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-        # control and status module
+    builder_args(parser)
-        self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
+    soc_core_args(parser)
-        self.add_csr("cas")
+    args = parser.parse_args()
 
-        # Add debug interface if the CPU has one ---------------------------------------------------
+    soc = BaseSoC(**soc_core_argdict(args))
-        if hasattr(self.cpu, "debug_bus"):
+    builder = Builder(soc, **builder_argdict(args))
-            self.register_mem(
+    builder.build(run=args.build)
-                name="vexriscv_debug",
-                address=0xf00f0000,
-                interface=self.cpu.debug_bus,
-                size=0x100)
 
-        # Memory mapped SPI Flash ------------------------------------------------------------------
+    if args.load:
-        self.submodules.spiflash = spi_flash.SpiFlash(
+        prog = soc.platform.create_programmer()
-            platform.request("spiflash"),
+        prog.load_bitstream(os.path.join(builder.gateware_dir, "top.sof"))
-            dummy=platform.spiflash_read_dummy_bits,
-            div=platform.spiflash_clock_div,
-            endianness=self.cpu.endianness)
-        self.add_csr("spiflash")
-        self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
-        self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
-        self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size)
-        self.register_mem("spiflash", self.mem_map["spiflash"],
-            self.spiflash.bus, size=platform.spiflash_total_size)
-        self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
-        self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
-        self.add_constant("DEVICE_TREE_IMAGE_FLASH_OFFSET",0x00000000)
-        self.add_constant("EMULATOR_IMAGE_FLASH_OFFSET",0x20000)
-        self.add_constant("KERNEL_IMAGE_FLASH_OFFSET",0x40000)
-        self.add_constant("ROOTFS_IMAGE_FLASH_OFFSET",0x5c0000)
 
-        # Take Ethernet Phy out of reset for SYSCLK of 125 Mhz
+if __name__ == "__main__":
-        gmii_rst_n = platform.request("gmii_rst_n")
+    main()
-        self.comb += [
-            gmii_rst_n.eq(1)
-        ]
-
-
-SoC = BaseSoC