targets/panol_logic_g2: replace with a minimal target.
This commit is contained in:
Florent Kermarrec
parent
99c04358bf
commit
19b12fd984
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@ -1,224 +1,61 @@
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# This file is Copyright (c) 2019 Tom Keddie <git@bronwenandtom.com>
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# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
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#!/usr/bin/env python3
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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# Support for the Pano Logic Zero Client G2
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from migen import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.interconnect import wishbone
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from litedram.modules import MT47H32M16
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from litedram.phy import s6ddrphy
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from litedram.core import ControllerSettings
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from gateware import cas
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from gateware import info
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from gateware import spi_flash
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# Support for the Pano Logic Zero Client G2
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import pano_logic_g2
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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def __init__(self, platform, clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sdram_half = ClockDomain()
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self.clock_domains.cd_sdram_full_wr = ClockDomain()
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self.clock_domains.cd_sdram_full_rd = ClockDomain()
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self.reset = Signal()
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# # #
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f0 = int(125e6)
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self.submodules.pll = pll = S6PLL(speedgrade=-2)
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pll.register_clkin(platform.request("clk125"), 125e6)
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pll.create_clkout(self.cd_sys, clk_freq)
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clk125 = platform.request(platform.default_clk_name)
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clk125a = Signal()
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# BaseSoC ------------------------------------------------------------------------------------------
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self.specials += Instance("IBUFG", i_I=clk125, o_O=clk125a)
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), **kwargs):
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platform = pano_logic_g2.Platform()
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clk125b = Signal()
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self.specials += Instance(
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"BUFIO2", p_DIVIDE=1,
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p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
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i_I=clk125a, o_DIVCLK=clk125b)
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unbuf_sdram_full = Signal()
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unbuf_sdram_half_a = Signal()
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unbuf_sdram_half_b = Signal()
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unbuf_encoder = Signal()
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unbuf_sys = Signal()
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unbuf_unused = Signal()
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# PLL signals
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pll_lckd = Signal()
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pll_fb = Signal()
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self.specials.pll = Instance(
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"PLL_ADV",
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name="crg_pll_adv",
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p_SIM_DEVICE="SPARTAN6", p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
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p_REF_JITTER=.01,
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i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
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p_DIVCLK_DIVIDE=1,
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# Input Clocks (125MHz)
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i_CLKIN1=clk125b,
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p_CLKIN1_PERIOD=platform.default_clk_period,
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i_CLKIN2=0,
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p_CLKIN2_PERIOD=0.,
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i_CLKINSEL=1,
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# Feedback
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# (1000MHz) vco
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i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
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p_CLK_FEEDBACK="CLKFBOUT",
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p_CLKFBOUT_MULT=8, p_CLKFBOUT_PHASE=0.,
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# (200MHz) sdram wr rd
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o_CLKOUT0=unbuf_sdram_full, p_CLKOUT0_DUTY_CYCLE=.5,
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p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=5,
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# (100MHz) unused
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o_CLKOUT1=unbuf_encoder, p_CLKOUT1_DUTY_CYCLE=.5,
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p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=10,
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# (100MHz) sdram_half - sdram dqs adr ctrl
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o_CLKOUT2=unbuf_sdram_half_a, p_CLKOUT2_DUTY_CYCLE=.5,
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p_CLKOUT2_PHASE=270., p_CLKOUT2_DIVIDE=10,
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# (100MHz) off-chip ddr
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o_CLKOUT3=unbuf_sdram_half_b, p_CLKOUT3_DUTY_CYCLE=.5,
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p_CLKOUT3_PHASE=250., p_CLKOUT3_DIVIDE=10,
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# (100MHz) unused
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o_CLKOUT4=unbuf_unused, p_CLKOUT4_DUTY_CYCLE=.5,
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p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=10,
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# ( 50MHz) sysclk
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o_CLKOUT5=unbuf_sys, p_CLKOUT5_DUTY_CYCLE=.5,
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p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=20,
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)
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# power on reset?
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reset = ~platform.request("cpu_reset") | self.reset
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self.clock_domains.cd_por = ClockDomain()
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por = Signal(max=1 << 11, reset=(1 << 11) - 1)
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self.sync.por += If(por != 0, por.eq(por - 1))
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self.specials += AsyncResetSynchronizer(self.cd_por, reset)
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# System clock - 50MHz
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self.specials += Instance("BUFG", name="sys_bufg", i_I=unbuf_sys, o_O=self.cd_sys.clk)
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self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | (por > 0))
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# SDRAM clocks
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# ------------------------------------------------------------------------------
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self.clk4x_wr_strb = Signal()
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self.clk4x_rd_strb = Signal()
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# sdram_full
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self.specials += Instance("BUFPLL", name="sdram_full_bufpll",
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p_DIVIDE=4,
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i_PLLIN=unbuf_sdram_full, i_GCLK=self.cd_sys.clk,
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i_LOCKED=pll_lckd,
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o_IOCLK=self.cd_sdram_full_wr.clk,
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o_SERDESSTROBE=self.clk4x_wr_strb)
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self.comb += [
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self.cd_sdram_full_rd.clk.eq(self.cd_sdram_full_wr.clk),
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self.clk4x_rd_strb.eq(self.clk4x_wr_strb),
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]
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# sdram_half
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self.specials += Instance("BUFG", name="sdram_half_a_bufpll", i_I=unbuf_sdram_half_a, o_O=self.cd_sdram_half.clk)
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clk_sdram_half_shifted = Signal()
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self.specials += Instance("BUFG", name="sdram_half_b_bufpll", i_I=unbuf_sdram_half_b, o_O=clk_sdram_half_shifted)
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output_clk = Signal()
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clk = platform.request("ddram_clock_b")
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self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
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p_INIT=0, p_SRTYPE="SYNC",
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i_D0=1, i_D1=0, i_S=0, i_R=0, i_CE=1,
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i_C0=clk_sdram_half_shifted,
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i_C1=~clk_sdram_half_shifted,
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o_Q=output_clk)
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self.specials += Instance("OBUFDS", i_I=output_clk, o_O=clk.p, o_OB=clk.n)
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from targets.utils import dict_set_max
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class BaseSoC(SoCSDRAM):
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mem_map = {**SoCSDRAM.mem_map, **{
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'spiflash': 0x20000000,
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}}
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def __init__(self, platform, **kwargs):
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dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
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dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
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sys_clk_freq = int(50e6)
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
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# DDR2 SDRAM -------------------------------------------------------------------------------
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if True:
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sdram_module = MT47H32M16(sys_clk_freq, "1:2")
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self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
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platform.request("ddram_b"),
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memtype = sdram_module.memtype,
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rd_bitslip = 0,
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wr_bitslip = 4,
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dqs_ddr_alignment="C0")
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self.add_csr("ddrphy")
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controller_settings = ControllerSettings(
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with_bandwidth=True)
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self.register_sdram(
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self.ddrphy,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings,
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controller_settings=controller_settings)
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self.comb += [
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self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
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self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
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]
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# Build --------------------------------------------------------------------------------------------
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# Basic peripherals ------------------------------------------------------------------------
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# info module
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self.submodules.info = info.Info(platform, self.__class__.__name__)
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self.add_csr("info")
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# control and status module
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self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
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self.add_csr("cas")
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Pano Logic G2")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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# Add debug interface if the CPU has one ---------------------------------------------------
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if hasattr(self.cpu, "debug_bus"):
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self.register_mem(
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name="vexriscv_debug",
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address=0xf00f0000,
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interface=self.cpu.debug_bus,
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size=0x100)
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soc = BaseSoC(**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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# Memory mapped SPI Flash ------------------------------------------------------------------
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self.submodules.spiflash = spi_flash.SpiFlash(
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platform.request("spiflash"),
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dummy=platform.spiflash_read_dummy_bits,
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div=platform.spiflash_clock_div,
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endianness=self.cpu.endianness)
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self.add_csr("spiflash")
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self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
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self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
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self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size)
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self.register_mem("spiflash", self.mem_map["spiflash"],
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self.spiflash.bus, size=platform.spiflash_total_size)
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self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
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self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
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self.add_constant("DEVICE_TREE_IMAGE_FLASH_OFFSET",0x00000000)
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self.add_constant("EMULATOR_IMAGE_FLASH_OFFSET",0x20000)
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self.add_constant("KERNEL_IMAGE_FLASH_OFFSET",0x40000)
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self.add_constant("ROOTFS_IMAGE_FLASH_OFFSET",0x5c0000)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, "top.sof"))
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# Take Ethernet Phy out of reset for SYSCLK of 125 Mhz
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gmii_rst_n = platform.request("gmii_rst_n")
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self.comb += [
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gmii_rst_n.eq(1)
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]
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SoC = BaseSoC
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if __name__ == "__main__":
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main()
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